Apparatus for generating test vector of semiconductor integrated circuit

ABSTRACT

A method for generating a test vector of a semiconductor integrated circuit including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. P2002-313172, filed on Oct.28, 2002; the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a delay fault test of a semiconductorintegrated circuit. More particularly, the invention relates to a methodof generating a test vector for a delay fault test and to a method ofanalyzing a delay fault in a semiconductor integrated circuit which hasfailed in a delay fault test.

2. Description of the Related Art

Verification of functions and timing in a semiconductor integratedcircuit, mainly, in a logic circuit product is performed by simulation.A test vector used in the simulation is used in a test for analysis oftiming in a test of the semiconductor integrated circuit. Moreover,automatic generation of a test vector for the delay fault test isexecuted in order to activate a critical path which has been identifiedby the timing analysis.

In the verification of timing in the semiconductor integrated circuit,confirmation is made as to whether delays in signals on each pathbreaches a timing at a target operation frequency. Since a path with alarge signal delay is assumed to easily breach timing and timingverification of a path is executed for the path with a large signaldelay, there is a case that object paths to be verified are centered onspecific circuit blocks and paths which have breached timing arecentered on specific circuit blocks. Moreover, there is a case that testvectors for delay fault tests exist only in specific regions in thesemiconductor integrated circuit.

On the other hand, there is dispersion of size and density inmanufacturing of a semiconductor integrated circuit. Also, there isstructural scattering in the semiconductor integrated circuit. Thestructural scattering may occur that a path, which is assumed atverification of timing during a design stage to easily breach timing,does not necessarily become an actual breach path, after thesemiconductor integrated circuit is actually manufactured. The timingbreach is generated on another path in some cases.

Accordingly, there have been requirements to execute the delay faulttest on a path which is selected so that the path is distributed allover the area of the semiconductor integrated circuit. However, noapparatus is available which generates a test vector by which a specificregion is tested by designating the specific region. Such apparatus isneeded to satisfy the requirements, on the semiconductor integratedcircuit.

The delay fault analysis of paths on the semiconductor integratedcircuit is examined, using a path with a delay fault test, to determinewhat cell has the delay fault in a plurality of cells forming a pathwith a delay fault. There has been no apparatus which generates a testvector by which a specific region is tested by designating the specificregion, which apparatus is needed to execute the above examination, onthe semiconductor integrated circuit.

SUMMARY OF THE INVENTION

An aspect of the present invention inheres in an apparatus forgenerating a test vector of a semiconductor integrated circuit accordingto embodiments of the present invention. The apparatus includes aretrieval-condition designation section designating a retrievalcondition configured to select a path on which a signal can betransmitted in the semiconductor integrated circuit, a path-listgeneration section executing a timing analysis of the semiconductorintegrated circuit based on circuit information of the semiconductorintegrated circuit, retrieving the path satisfying the retrievalcondition, and generating a path list in which cells composing theretrieved path are put in order of executing the timing analysis, atest-vector generation section generating a test vector configured totest a path delay fault of the semiconductor integrated circuit based onthe path list, an ending-condition designation section designating anending condition configured to end generation of the test vector whenthe path in the path list for the test vector is distributed over thesemiconductor integrated circuit, and an ending-condition determinationon judgment section stopping generation of the path list when the endingcondition is satisfied.

Another aspect of the present invention inheres in an apparatus fordebugging an failure of a semiconductor integrated circuit according toembodiments of the present invention. The apparatus includes a cell-listgeneration section generating a list of cells composing a path in thesemiconductor integrated circuit with a delay fault based on a testresult of whether the delay fault is generated on the path, aretrieval-condition designation section designating a retrievalcondition configured to retrieve a fault-cell searching path, whichincludes a part of the path with the delay fault, a path-list generationsection for fault-cell searching, which retrieves the fault-cellsearching path based on the retrieval condition, and generates afault-cell searching path list in which cells composing the retrievedfault-cell searching path are put in an order of transmitting a signal,a test-vector generation section for fault-cell searching, whichgenerates a test vector based on the fault-cell searching path list, anending-condition designation section designating an ending conditionconfigured to end generation of the test vector, and an ending-conditiondetermination or judgment section stopping generation of the path listwhen the ending condition is satisfied.

Still another aspect of the present invention inheres in acomputer-implemented method for generating a test vector of asemiconductor integrated circuit according to embodiments of the presentinvention. The method includes designating a retrieval conditionconfigured to select a path on which a signal can be transmitted in thesemiconductor integrated circuit, executing a timing analysis of thesemiconductor integrated circuit based on circuit information of thesemiconductor integrated circuit, retrieving the path satisfying theretrieval condition, and generating a path list in which cells composingthe retrieved path are put in an order of executing the timing analysis,generating a test vector configured to test a path delay fault of thesemiconductor integrated circuit based on the path list, designating anending condition configured to end generation of the test vector whenthe path in the path list for the test vector is distributed over thesemiconductor integrated circuit, and stopping generation of the pathlist when the ending condition is satisfied.

Still another aspect of the present invention inheres in a computerprogram product to be executed by a computer for generating a testvector of a semiconductor integrated circuit according to embodiments ofthe present invention. The program product includes instructionsdesignating a retrieval condition configured to select a path on which asignal can be transmitted in the semiconductor integrated circuit,instructions executing a timing analysis of the semiconductor integratedcircuit based on circuit information of the semiconductor integratedcircuit, retrieving the path satisfying the retrieval condition, andgenerating a path list in which cells composing the retrieved path areput in an order of executing the timing analysis, instructionsgenerating a test vector configured to test a path delay fault of thesemiconductor integrated circuit based on the path list instructionsdesignating an ending condition configured to end generation of the testvector when the path in the path list for the test vector is distributedover the semiconductor integrated circuit, and instructions stoppinggeneration of the path list when the ending condition is satisfied.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a manufacturing method of a semiconductorintegrated circuit according to a first embodiment;

FIG. 2 is a block diagram of an apparatus for generating a test vectoraccording to the first embodiment;

FIG. 3 is a flow chart of a test-vector generating method according tothe first embodiment;

FIG. 4 is a block diagram of an apparatus for generating a test vectoraccording to a variant 1 of the first embodiment;

FIG. 5 is a block diagram of an apparatus for generating a test vectoraccording to a variant 2 of the first embodiment;

FIG. 6 is a flow chart of a test-vector generating method according tothe variant 2 of the first embodiment;

FIG. 7 is a block diagram of an apparatus for generating a test vectoraccording to a variant 3 of the first embodiment;

FIG. 8 is a block diagram of an apparatus for generating a test vectoraccording to a variant 4 of the first embodiment;

FIG. 9 is a block diagram of an apparatus for generating a test vectoraccording to a variant 5 of the first embodiment;

FIG. 10 is a block diagram of a fault analysis apparatus of asemiconductor circuit according to a second embodiment;

FIG. 11 is a flow chart of a fault analysis method of a semiconductorcircuit according to the second embodiment;

FIG. 12 is a block diagram of a fault analysis apparatus of asemiconductor circuit according to a variant 1 of the second embodiment;

FIG. 13 is a block diagram of a fault analysis apparatus of asemiconductor circuit according to a variant 2 of the second embodiment;

FIG. 14 is a block diagram of a fault analysis apparatus of asemiconductor circuit according to a variant 3 of the second embodiment;

FIG. 15 is a data structure of a retrieval condition for a test-vectorgenerating method according to an example 1 of the first embodiment;

FIG. 16 is a data structure of an ending condition for the test-vectorgenerating method according to the example 1 of the first embodiment;

FIG. 17 is a data structure of a path list for the test-vectorgenerating method according to the example 1 of the first embodiment;

FIG. 18 is a data structure of test-vector generation information forthe test-vector generating method according to the example 1 of thefirst embodiment;

FIG. 19 is a screen image of a semiconductor integrated circuit of atest-vector generating method according to the example 2 of the firstembodiment, in which the circuit is divided into regions and the regionscan be designated;

FIG. 20 is a block diagram of the semiconductor integrated circuit ofthe test-vector generating method according to the example 2 of thefirst embodiment;

FIG. 21 is a screen image of the semiconductor integrated circuit of thetest-vector generating method according to the example 2 of the firstembodiment, in which the circuit is divided into regions equally in thevertical and horizontal directions and the regions can be designated;

FIG. 22 is a screen image of the semiconductor integrated circuit of thetest-vector generating method according to the example 2 of the firstembodiment, in which the circuit is divided into regions with equal areaand the regions can be designated;

FIG. 23 is an explanatory view of a method by which a screen image ofthe semiconductor integrated circuit of the test-vector generatingmethod according to the example 2 of the first embodiment is dividedinto regions, the regions can be designated, and screen images of pathsare superposed on the screen image of the circuit;

FIG. 24 is a data structure of definition of coverage for thetest-vector generating method according to the example 2 of the firstembodiment;

FIG. 25 is a data structure of a retrieval condition, including acoverage rate, for the test-vector generating method according to theexample 2 of the first embodiment;

FIG. 26 is a data structure of an ending condition, including thecoverage rate, for the test-vector generating method according to theexample 2 of the first embodiment;

FIG. 27 is an explanatory view of the test-vector generating methodaccording to the example 2 of the first embodiment;

FIG. 28 is an explanatory view of the test-vector generating methodaccording to the example 2 of the first embodiment;

FIG. 29 is an explanatory view of the test-vector generating methodaccording to the example 2 of the first embodiment;

FIG. 30 is a data structure of a retrieval condition for a test-vectorgenerating method according to an example 3 of the first embodiment;

FIG. 31 is a data structure of a pin-name list, including circuitinformation, for a test-vector generating method according to an example4 of the first embodiment;

FIG. 32 is a data structure of a delimiter value for a test-vectorgenerating method according to an example 5 of the first embodiment;

FIG. 33 is an explanatory view of a method by which a screen image ofpaths for the test-vector generating method according to the example 5of the first embodiment is displayed, based on the delimiter value;

FIG. 34 is a data structure of a test result of a fault analysis methodof a semiconductor integrated circuit according to an example 1 of thesecond embodiment;

FIG. 35 is a data structure of a cell list for the fault analysis methodof a semiconductor integrated circuit according to the example 1 of thesecond embodiment;

FIG. 36 is a data structure of a retrieval condition for the faultanalysis method of a semiconductor integrated circuit according to theexample 1 of the second embodiment;

FIG. 37 is a data structure of an ending condition for the faultanalysis method of a semiconductor integrated circuit according to theexample 1 of the second embodiment;

FIG. 38 is a data structure of a path list for the fault analysis methodof a semiconductor integrated circuit according to the example 1 of thesecond embodiment;

FIG. 39 is an explanatory view of a path with a fault and a path forfault analysis in a test for the fault analysis method according to theexample 1 of the second embodiment;

FIG. 40 is a data structure of a pin-coordinate information for a faultanalysis method of a semiconductor integrated circuit according to anexample 2 of the second embodiment;

FIG. 41 is a data structure of a retrieval condition for a faultanalysis method of a semiconductor integrated circuit according to anexample 3 of the second embodiment;

FIG. 42 is an explanatory view of a path with a fault and a path forfault analysis in a test for the fault analysis method according to theexample 3 of the second embodiment;

FIG. 43 is an explanatory view of a fault analysis method of asemiconductor integrated circuit according to an example 4 of the secondembodiment;

FIG. 44 is an explanatory view of the fault analysis method of thesemiconductor integrated circuit according to the example 4 of thesecond embodiment;

FIG. 45 is an explanatory view of the fault analysis method of thesemiconductor integrated circuit according to the example 4 of thesecond embodiment; and

FIG. 46 is an explanatory view of wafer distribution of a semiconductorintegrated circuit having paths with a fault in a test for a faultanalysis method of a semiconductor integrated circuit according to anexample 5 of the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention will be described withreference to the accompanying drawings. It is to be noted that the sameor similar reference numerals are applied to the same or similar partsand elements throughout the drawings, and the description of the same orsimilar parts and elements will be omitted or simplified.

(First Embodiment)

In a method for designing and manufacturing a semiconductor integratedcircuit according to the first embodiment, specifications of thesemiconductor integrated circuit are input at STEP S1, as shown inFIG. 1. At STEP S2, logic synthesis is executed, based on thespecifications of the semiconductor integrated circuit to generate alogical expression. Based on the logical expression, a netlist isgenerated, using circuit blocks and cells. Based on the netlist, placingand routing for the circuit blocks and the cells is executed to generatea layout pattern of the semiconductor integrated circuit.

A test pattern is generated at STEP S3. A test vector 1 is generated,based on the test pattern. The test vector 1 by which a specific regionis tested by designating the specific region on the semiconductorintegrated circuit is generated in order to execute the delay fault testover all of the area of the semiconductor integrated circuit, to theextent possible.

The test vector 1 includes; a preparation vector; a system clock vector;and a detection vector. Initial logical-values of external pins andinternal pins of the semiconductor integrated circuit can be set, usingthe preparation vector. Using the system clock vector, control signalsare input, not only from the clock line, but also from arbitraryexternal pins and arbitrary internal pins to the semiconductorintegrated circuit. The initial logical-values of the external and theinternal pins are set, using the preparation vector, and the logic ofthe external and the internal pins are controlled, using the systemclock vector, to activate a desired path of the semiconductor integratedcircuit and to operate the cells and the circuit blocks on the path. Inthe detection vector, the expectation values which are expected to beoutput from the cells and the circuit blocks, which have been operatedbased on the preparation vector and the system clock vector, to theexternal and the internal pins are arranged. Simulation is executed forverification of the functions and the timing in a semiconductorintegrated circuit. The simulation is executed, based on the testpattern. The test vector 1 is used in the simulation.

It is judged or determined at STEP S4 whether a logical operation valuewhich is output based on the preparation vector and the system clockvector is in agreement with the expectation value based on the detectionvector. The processing proceeds to STEP S5 when there is an agreementbetween the logical operation value and the expectation value and theprocessing returns to STEP S2 when there is no agreement between thelogical operation value and the expectation value for correcting thenetlist and the layout pattern of the semiconductor integrated circuit

At STEP S5, a semiconductor substrate is processed and the semiconductorintegrated circuit for which operation tests can be conducted ismanufactured.

The delay fault test of the manufactured semiconductor integratedcircuit is executed at STEP S6. The test vector 1 is used for the delayfault test at STEP S6. Here, a delay fault test may be executed, usingthe corresponding test vector 1, especially, for a critical path whichhas been identified as a result of verification for timing at STEP S3.The test vector 1, by which a specific region is tested by designatingthe specific region on the semiconductor integrated circuit, may begenerated in order to execute the delay fault test over all of the areaof the semiconductor integrated circuit, to the extent possible. A testfor confirming whether a signal corresponding to the expectation valueis output or not within a predetermined delay time, which is defined sothat there is no breach in the operation frequency of the semiconductorintegrated circuit, is executed for obtaining a measurement value of thedelay time. Moreover, the test vector, which activates the criticalpath, for the delay fault test may be generated at STEP S6.

It is determined or judged at STEP S7 whether the delay fault occurs bythe activated path. Based on the decision, it is determined or judgedwhether a fault analysis of the semiconductor integrated circuit isrequired or not. When a delay fault occurs, it is determined or judgedthat a fault analysis is required and the processing proceeds to STEPS8. When a delay fault does not occur, it is determined or judged that afault analysis is not required and the processing proceeds to STEP S9 atwhich the semiconductor integrated circuit is completed. Accordingly,the method for manufacturing the semiconductor integrated circuit iscompleted.

The fault analysis of a fault path on which the delay fault occurs isexecuted at STEP S8. In the delay fault analysis of the path, the faultpath is estimated, using a test vector which failed in the delay faulttest and circuit information on the semiconductor integrated circuit.Alternatively, the fault path is identified, using a path input atgeneration of the test vector which failed in the test when a testvector for the delay fault is generated.

In order to determine or judge what circuit blocks and what cells of thesemiconductor integrated circuit have been tested by the fault path, thefault path can be displayed on a screen displaying the layout patternwhen information on the fault path is added to the layout pattern of thesemiconductor integrated circuit. It is possible to limit a range inwhich the fault path exists.

However, it is impossible to identify what cell has the delay fault,because the fault path has a configuration in which a plurality of cellsis connected. In order to determine the cell which causes the delayfault, a new path, which shares a part of the cells with the fault path,for fault-cell searching is searched. A test vector which activates thepath for fault-cell searching is generated. The delay fault test of thepath for fault-cell searching is executed, using the test vector.

Test vectors for a plurality of paths, each of which shares respectivelydifferent parts of the cells with the fault path, for fault-cellsearching are generated for the test. At this time, only the testvectors including the cells which cause the delay fault fail thetesting. Then, the range of cells which cause failure is narrowed tospecify the cell which is finally identified as the cell which causesthe failure.

(Apparatus for Generating a Test Vector)

An apparatus for generating a test vector according to the firstembodiment is a computer. As shown in FIG. 2, the computer includes: aretrieval-condition designation section 11; an ending-conditiondesignation section 12; a circuit-information storage section 13; apath-list generation section 14; a path-list storage section 15; atest-vector generation section 16; a test-vector storage section 17; atest-vector-generation information storage section 18; anending-condition determination or judgment section 19; an input section204; and an output section 206.

In the retrieval-condition designation section 11, a retrieval conditionis designated for selecting a path on which a signal can be transmittedin the semiconductor integrated circuit.

In the circuit-information storage section 13, circuit information onthe semiconductor integrated circuit is recorded so that the computercan read the information.

In the path-list generation section 14, timing analysis is executed,based on the circuit information on the semiconductor integratedcircuit, a path satisfing the retrieval conditions is retrieved, and apath-list in which cells forming a retrieved path are arranged in theorder of executing the timing analysis of the cells forming theretrieved path is generated.

In the path-list storage section 15, the generated path-list is recordedso that the computer can read the list.

In the test-vector generation section 16, the test vector 1 andtest-vector-generation information are generated for the delay faulttest of the path on the semiconductor integrated circuit, based on thepath-list.

In the test-vector storage section 17, the generated test vector 1 isrecorded so that the computer can read the vector.

In the test-vector-generation information storage section 18, thegenerated test-vector-generation information is recorded so that thecomputer can read the vector.

In the ending-condition designation section 12, an ending condition isdesignated for ending generation of the test vector 1. Moreover, theending-condition designation section 12 includes acoverage-judging-condition designation section 201 and a coverage-ratedefinition section 202. When the ending condition is satisfied in theending-condition determination or judgment section 19, generation of thepath-list in the path-list generation section 14 is stopped.

The coverage-judging-condition designation section 201 divides thesemiconductor integrated circuit into a plurality of regions, anddesignates a coverage determining or judging condition for determiningor judging that a region is covered by the path-list path, which is thebase of the generated test vector. In the ending-condition determinationor judgment section 19, judging or determination of covered regions isexecuted by assuming that the coverage judging condition is treated asan ending condition. The path-list generation section 14 and thetest-vector generation section 16 executed judging of covered regions,assuming that the coverage judging condition is treated as a retrievalcondition and a path-list or a test vector of a path which is judged tobe covered is extracted. A coverage judging condition considers severalfactors. For example, the number of paths passing the region, the logicelements in the path in the region, the wiring length of the path, thenumber of vias and contacts is larger than a predetermined value, andthat a layer of wiring on the path and via is a predetermined layer.Tests can be suitably executed for each region by using a concept of thecoverage. That is, it is difficult to execute suitable testing of aregion, using a test vector for one path, when the path passes veryclose to the edge of the region. Then, a path is required to pass theregion so that suitable testing can be executed. The concept of thecoverage can satisfy the above requirement.

The coverage-rate definition section 202 designates the coverage rate asa ratio of the number of the regions which are judged to be covered tothe total number of regions. The ending-condition designation section 12designates the ending condition as that the coverage rate, as a resultof the generation of the test vector, of the path is larger than thepredetermined coverage rate. The retrieval-condition designation section11 designates the retrieval condition as that the coverage rate of thepath is larger than the predetermined coverage rate.

The input section 204 and the output section 206 exchange data betweenthe apparatus for generating a test vector, and external apparatuss oroperators.

A plurality of test vectors, which are based on a plurality of pathswhich have coverage rates larger than a predetermined value, can begenerated by using coverage rates, in the selected chip regions, ofpaths, which have succeeded in generation of test vectors, as theretrieval condition and the ending conditions. Thereby, test vectors, bywhich a chip can be uniformly tested with high quality can be generated,because paths are not concentrated in an unbalanced manner on a part ofthe regions on the chip.

An apparatus for generating a test vector may be a computer and anapparatus for generating a test vector may be provided by executingprocedures in accordance with a program in the computer.

(Test-Vector Generating Method)

The test-vector-generating method according to the first embodiment canbe executed in a computer. At STEP 11, circuit information is input fromthe circuit-information storage section 13 to the path-list generationsection 14 in the test-vector-generating method according to the firstembodiment, as shown in FIG. 3. The circuit information may be a netlistdescribing connecting information for the circuit blocks and the cells.When more detailed routing of layout information for the circuit blocksand the cells is designated as a retrieval condition, the circuitinformation may be the layout pattern of the semiconductor integratedcircuit, though the layout pattern is the routing information for thecircuit blocks and the cells.

Then, the ending-condition designation section 12 generates a condition,at STEP S12, which ends the generation process of the test vector 1. Atgeneration of the ending condition, the ending-condition designationsection 12 generates and designates a numerical value which is an endingcondition which is, for example, the number of test vectors 1 whichsucceed in generation, the sum of the logic elements which the generatedtest vectors 1 pass, and the sum of the start points and the end pointsthat the generated test vectors 1 are required to exceed thepredetermined value.

At STEP 13, the retrieval-condition designation section 11 generates acondition on which a path of the logic circuit to be tested isretrieved. At generation of the retrieval condition, the retrievalcondition for a first retrieval operation and the retrieval conditionsfor retrieval operations after a second retrieval operation aregenerated.

At generation of the retrieval condition for the first retrievaloperation, the retrieval-condition designation section 11 generates anddesignates a specific ranking as the retrieval condition, wherein theranking of the path is required to be higher than the specific ranking,when the paths are arranged in the decreasing order of, for example,signal-propagation-time, that is, delay time on the path.

At generation of the retrieval condition for retrieval operations afterthe second operation, the retrieval-condition designation section 11generates and designates a retrieval condition “the interior of thesemiconductor integrated circuit is divided to generate divided regionsand a path is required to pass through the divided regions where no pathhas passed, determined by using a result of generation of a path whichhas succeeded in generation of the test vector according to theretrieval conditions for retrievals at the first retrieval operation andafter the second operations”.

Designation of the number of total steps which is the sum of the numbersof cells on the paths, designation of the total wiring length of thewiring for signal transmission on the path, designation of the number ofvias or of contacts on the path of a signal transmission line, anddesignation of a layer to which wiring or the vias belong are assumed asother retrieval conditions for the first retrieval operation.

Moreover, a coverage condition can be set in which the coverage isdefined so that a path passes a divided region. The total number ofsteps and the total wiring lengths on the path, the number of vias andcontacts, designation of a layer to which wiring or the vias belong, andthe like in the divided region of an target are considered as thecoverage condition.

Here, the executing order of STEPs S11, S12 and S13 may be arbitrary, orthe above STEP S11, S12, and S13 may be simultaneously executed.

Subsequently, a path-list for paths of an object of the test-patterngeneration on the semiconductor integrated circuit is generated at STEPS14 in the path-list generation section 14 under a timing analysis ofthe semiconductor integrated circuit, based on the designated retrievalcondition. The path list is stored in the path-list storage section 15.

It is judged or determined at STEP S15 whether the path list for thepath of a target of the test pattern generation has been newlyextracted. In the flow chart of FIG. 3, there is a loop in which theprocessing proceeds from STEP S13 to STEP S18 and, then, returns to STEPS13. Preferably, a retrieval condition is designated at a first cycle ofthe loop in such a way that a path-list of new paths is generated andthe processing can proceed to STEP S16, based on the designation result.

At STEP S16, the path-list stored in the storage section 15 and circuitinformation on the semiconductor integrated circuit stored in thecircuit-information storage section 13 are input to the test-vectorgeneration section 16. Then, test vectors by which delay faults can bedetected are generated for each path. The circuit information to beinput may be different in the degree of details and the level of thedescription form that of the circuit information used for generatingpath lists at STEP S14. The test-vector generation section 16 recordsand stores the test vectors, which have succeeded in the generation, inthe test-vector storage section 17. Moreover, the test-vector-generationinformation as to whether test vectors are successfully generated foreach path is recorded and stored in the test-vector-generationinformation storage section 18.

At STEP S17, the ending-condition judgment section 19 judges ordetermines whether the current situations of generation of test vectors,stored in the test-vector-generation information storage section 18,satisfy the ending requirements designated at STEP 12 for designation ofan ending condition.

At STEP S18, the processing returns to STEP S13 when the currentsituations of generation of test vectors, stored in thetest-vector-generation information storage section 18, do not satisfythe ending requirements. At STEP S13, a retrieval condition is updatedto a new retrieval condition for designation. The new retrievalcondition is changed so that a test vector is more successfullygenerated in comparison with the case using the previous retrievalcondition. Subsequently, a new path is retrieved at STEP S14 to generatea path-list of the path again, based on the new retrieval condition. Itis judged at STEP S15 whether a path-list of new paths is generated,based on the new retrieval condition. When the path-list of new paths isgenerated, the processing proceeds to STEP S16. When the path-list ofnew paths is not generated, the processing proceeds to STEP S19. At STEPS19, a final test-vector-generation information is output to an externalmemory. Moreover, a final test vector is output to the external memoryat STEP S20. Thereafter, the test-vector generating method is ended.Here, the processing may return to STEP S13 again when the path-list ofthe new paths is not generated.

At STEP S18, the processing proceeds to STEP S19, at which a finaltest-vector-generation information is output to an external memory whenthe current situations of generation of test vectors, stored in thetest-vector-generation information storage section 18, satisfy theending requirements. A final test vector is output to the externalmemory at STEP S20. That is, the processing is ended in the test-vectorgenerating method when another path satisfying the retrieval conditionis not newly retrieved, or when generation situations of test vectorssatisfy the ending condition.

Thus, the test-vector generating method can be highly automated and thequality of the generated test vector can be improved according to theapparatus for generating a test vector, because a test vector for a pathcan be generated by executing the test-vector generating method, usingthe retrieval condition and the ending condition. Moreover, in the past,the period required for generating the test vector has been severalweeks because substantial manpower was required. However, the periodaccording to the invention is only several days.

For the test-vector generating method, a program which can be executedas a procedure by a computer, for generating the test vector is made.The test-vector generating method can be executed the program forgenerating the test vector.

(Variant 1 of the First Embodiment)

In an apparatus for generating a test vector according to the firstembodiment of FIG. 2, a chip-region designation section 20 is added tothe ending-condition designation section 12 of the apparatus forgenerating a test vector, as shown in FIG. 4. STEP S13 of thetest-vector generating method according to the first embodiment shown inFIG. 3 is expanded and changed in the test-vector generating methodaccording to a variant 1 of the first embodiment.

The chip-region designation section 20 reads information on the logiccircuit of the semiconductor integrated circuit from thecircuit-information storage section 13. The chip-region designationsection 20 generates a screen image of the entire chip area of thesemiconductor integrated circuit, or a part of the logic circuit (aso-called user logic section except for circuit blocks which aregenerally built in) which is a part of the chip area and an object forforming a test vector for a path delay-fault test. The screen image is adisplay section of the chip-region designation section 20 which anoperator of the apparatus for generating a test vector can recognize.Then, the chip-region designation section 20 is configured to generateregions which divide the screen image of the logic circuit part which isthe object for forming a test vector. According to a method for dividingthe screen image, the section 20 decides and designates a number ofdivisions in the vertical direction and in the horizontal one of thescreen image of the logic circuit part, respectively, and the screenimage of the logic circuit part is equally divided into the designatednumbers of regions in both directions for display. The chip-regiondesignation section 20 generates display-image division informationwhich has display positions for line segments for dividing the screenimage of the logic circuit part on the screen image. The chip regionspecification part 20 divides the screen image of the logic circuit partby superposing the screen image of line segments for divisions on thescreen image of the logic circuit part, based on the display-imagedivision information.

The chip-region designation section 20 displays the screen image of thesemiconductor integrated circuit, wherein the image is divided into theregions. Using the display, an operator of the apparatus for generatinga test vector is requested to designate a divided region, based on thescreen image of the semiconductor integrated circuit. Preferably, ascreen image of a path which has already succeeded in generation of atest vector is superposed and displayed on the screen image of thesemiconductor integrated circuit when the operator is requested todesignate a divided region. By seeing a display screen on which thescreen image of a path is superposed on the screen image of thesemiconductor integrated circuit, the operator can instantaneouslydiscriminate between a divided region in which a path for a test vectoris generated is arranged and a divided region in which a path for a testvector is not generated. The operator of the apparatus for generating atest vector designates a divided region in which the operator desires toarrange a path, responding to a request of the chip-region designationsection 20, and inputs the designated specific divided region. Theoperator is required only to select one of the regions, in which testvectors have not yet been generated, as a region in which the path isdesired to be arranged. Preferably, the output section and the inputsection are an input and output section such as an integral touch panel.A touch panel is used because a screen image is required to be displayedon a screen as an output and, at the same time, input is required to beexecuted on the screen. An intent of the operator to designate aspecific region is realized when the operator touches a screen image inthe specific region displayed on the touch panel so as to provide aninput.

Retrieval-condition designation section 11 designates a retrievalcondition by which a designated path arranged in the designated regioncan be retrieved, based on the fact that the specific input region isdesignated. In the retrieval-condition designation section 11, a deviceuser explicitly designates a region in which the user desires to arrangea path on the displayed semiconductor integrated circuit and a retrievalcondition to be recreated is that a path is arranged in the designatedregion. In the path-list generation section 14, generation is executed,based on the recreated retrieval condition.

Here, in the retrieval-condition designation section 11, a retrievalcondition that a path is arranged in a region, in which a path had notbeen previously arranged is automatically designated without dependingon an operator input and the retrieval condition may be recreated.Thereby, paths can be uniformly arranged on the semiconductor integratedcircuit.

In the chip-region designation section 20, a single region has beendesignated as described above. But, not only a single region, but also aplurality of regions can be designated and a priority among theplurality of regions can be designated. Thereby, paths arranged in eachregion are retrieved in a decreasing order of priority. Moreover,designation of regions in the chip-region designation section 20 may beperformed whenever the processing returns to STEP S13, or after the loopin the flow chart of FIG. 3 is repeated a predetermined number of times.That is, operations in the chip-region designation section 20 can beassumed to be operations following designation of a retrieval conditionat STEP S13 or to be operations included in operations at STEP S13.

Thus, situations for generation of test vectors are displayed atdesignation of a retrieval condition at STEP S13 to allow an operator toconfirm the situations, or to designate conditions, such as a priority,at the following generation of test vectors. Accordingly, a set of testvectors which are finally generated can be adjusted according to theintention of the device user.

Moreover, the operator designates a region in which the operator desiresto form a test vector in a path, and, at the same time, repeatedlyselects a new path while changing the retrieval condition which theapparatus for generating a test vector has designated. Thereby, a higherquality test vector which is finally generated can be obtained by theoperator's designation of regions.

(Variant 2 of the First Embodiment)

An apparatus for generating a test vector according to a second variantof the first embodiment has a configuration, as shown in FIG. 5, inwhich a retrieval-condition designation section 11 corresponding to aretrieval condition in the apparatus for generating a test vectoraccording to the first embodiment shown in FIG. 2. The apparatus of thesecond variant includes a circuit-information setting section 21; aretrieval-priority decision section 22; and a circuit-informationchanging section 23.

In the circuit-information setting section 21, a retrieval item relatingto the circuit information and a setting range for path retrievingcorresponding to the retrieval item are set. The circuit-informationsetting section 21 selects an item of a retrieval condition, as towhether a path is extracted by a retrieval based on a plurality of itemsrelating to process and design. The circuit-information setting section21 decides and sets a target value which an extracted cell is requiredto have for the gauge. The following combination is assumed to beconsidered. For example, the items relating to process and design, andthe gauges for the items and the target values. When the item is a pinname of a cell, the gauge and the target value are a specific pin nameof the start point or the end point of a path. When the item is wiring,the gauge is a sum of the wiring length of the wiring for a signal routeof a path and the target value is the range of lengths, such as 2 mm ormore. When the item is via, the gauge is a number of vias which providea signal route of a path, and the target value is the range of a numbersuch as 700 or more. When the item is a contact, the gauge and thetarget value can be treated in a similar manner to the case of the via.When the item is a layer of wiring and the via, the gauge and the targetvalue are such that the signal route of the path includes the layer ofthe wiring and the via. When the target is the number of steps of thepath, the gauge is a number of cells forming the path, and the targetvalue is the range of numbers such as 20 or more. Here, a plurality ofgauges and a plurality of target values may be set for one item.Moreover, a plurality of target values may be set for one gauge.

In the retrieval-priority decision section 22, a priority is decidedamong combinations of retrieval items to be satisfied by a path to beretrieved. In the retrieval-priority decision section 22, precedencesuch as the priority determining a cycle at which a retrieval conditionis adopted is set as an item gauge target value for process and designto be adopted as a retrieval condition to be updated every cycle in theloop of FIG. 6.

In the circuit-information changing section 23, a set value at thecircuit-information setting section 21 is relieved and a new path-listor a new test vector is more easily generated when a new path-list isnot generated in the path-list generation section 14, or when a new testvector is not generated in the test-vector generation section 16. In thecircuit-information changing section 23, a retrieval condition isrecreated and relieved when a path is not selected, based on a retrievalcondition, or when generation of a test vector for a selected pathresults in failure.

That is, the retrieval condition includes: a circuit-informationcondition; a retrieval-priority condition; and a circuit-informationchanging condition. The circuit-information condition includes: aretrieval item concerning circuit information; and a set valuecorresponding to the retrieval item and determining a range in which apath is retrieved. The retrieval-order condition includes prioritiesamong combinations of retrieval items upon determination of a path to beretrieved. The circuit-information changing condition includes arelieved set value by which a new path-list or a new test vector is moreeasily generated, when a new path-list is not generated in the path-listgeneration section 14, or when a new test vector is not generated in thetest-vector generation section 16.

Since the retrieval-condition designation section 11 includes thecircuit-information setting section 21, the retrieval-priority decisionsection 22, and the circuit-information changing section 23, theretrieval condition can be relieved and updated. For example, a largenumber of items are adopted as a retrieval condition for the first cycleand items which have been adopted can be deleted from the retrievalcondition at cycles after the second cycle. Moreover, a target valuewith which a path is not easily extracted is adopted as the retrievalcondition of the first cycle, and a target value which is changed sothat a path is more easily extracted can be adopted at cycles after thesecond cycle, based on the same gauges for the same items with those forthe target value which have already been adopted.

Here, it is obvious that the retrieval-condition designation section 11can be provided with all sections of the circuit-information settingsection 21, the retrieval-priority decision section 22, and that thecircuit-information changing section 23, and the section 11 can includeat least one of the sections 21-23.

The test-vector generating method according to the second variant of thefirst embodiment is obtained by adding STEPs S21 and S22 to thetest-vector generating method according to the first embodiment shown inFIG. 3, as shown in FIG. 6. Processing by which a retrieval condition isrelieved is performed at STEP S22 in the test-vector generating methodaccording to the second variant of the first embodiment when retrievalof a new path, based on a newly updated retrieval condition, orgeneration of a test vector result in a failure.

When it is decided at STEP S15 that extraction of a new path has failedat generation of the path-list of STEP S14, the processing proceeds toSTEP S22 and the path-list generation section 14 sets a failed-retrievalflag in the path-list storage section 15. Similarly, when it is decidedat STEP S21 that generation of a new test vector has failed atgeneration of the test vector of STEP S16, the processing proceeds toSTEP S22 and the test-vector generation section 16 sets afailed-retrieval flag in the test-vector storage section 17.

At STEP S22, the circuit-information changing section 23 detects thefailed-retrieval flag for relieving the retrieval condition. By thisoperation, while changing the retrieval condition, selection of a newpath can be repeatedly executed.

As described above, an operator can adjust the quality of the testvector which is finally generated in order to obtain a higher qualitytest vector, because a new path can be repeatedly selected whilechanging the designated retrieval condition and a test vector for aselected path can be repeatedly generated while changing the condition,in the process for generation of a test vector.

(Variant 3 of the First Embodiment)

An apparatus for generating a test vector according to a third variantof the first embodiment has a configuration, as shown in FIG. 7, inwhich an apparatus for generating a test vector corresponding to thesecond variant of the first embodiment shown in FIG. 5. The thirdvariant further includes: a chip-region designation section 20; apin-name-list providing section 25; a pin-list storage section 26; acircuit-information extraction section 24; and a circuit-information foreach pin-list storage section 27.

In the pin-name-list providing section 25, a pin-name list extractingpin names of cells in the designated regions is compiled, based on thedetailed placing and routing of layout information for cells in thecircuit information on the designated regions in the chip. In thecircuit-information extraction section 24, circuit information accordingto the retrieval item is extracted for each pin-name list.

A flow chart for a method which generates a test vector is basically thesame as that of FIG. 6. In the chip-region designation section 20, aregion in the chip is designated. The pin-name list is made in thepin-name-list providing section 25, using region information on thedesignated region and circuit information stored in thecircuit-information storage section 13. The compiled pin-name list isstored in the pin-list storage section 26. In the path-list generationsection 14, timing analysis is executed, based on the circuitinformation according to the pin-name list for each retrieval item, anda path covering the designated region is retrieved.

Based on data of circuit information in the circuit-information storagesection 13, the circuit-information extraction section 24 extractscircuit information with regard to an item, which is set in thecircuit-information setting section 21, in each pin-name list which isstored in the pin-list storage section 26. Here, the circuit informationfor each pin-name list is, for example, a wiring length of each wiringwhich is connected to each pin corresponding to each pin name describedfor each pin-name list. Moreover, the circuit information in eachpin-name list is information such as the names of the wiring layers foreach wiring which is connected to each pin corresponding to each pinname described for each pin-name list. The extracted circuit informationis stored in the circuit-information for each pin-list storage section27.

Thus, the retrieval-condition designation section 11 and an operator canadjust the quality of the test vector which is finally generated inorder to obtain a higher quality test vector, because information suchas a pin-name list for a selected region, a wiring length and a wiringlayer corresponding the pin-name list can be automatically obtained whenthe chip-region designation section 20 selects a region for which a testvector is required to be made in the test-vector generating method.According to an adjustment method, a retrieval condition of a path maybe designated so that a pin to which specific wiring having, forexample, the longest wiring length is connected is included.

(Variant 4 of the First Embodiment)

In an apparatus for generating a test vector according to a fourthvariant of the first embodiment, a pin list input from a pin-liststorage section 26 and circuit information for each pin list input froma circuit-information for each pin-list storage section 27 are furtherinput to a path-list generation section 14 corresponding to thepath-list generation section 14 in the apparatus for generating a testvector according to the third variant of the first embodiment shown inFIG. 7, as shown in FIG. 8.

The chip-region designation section 20 designates a region in the chip.The pin-name-list providing section 25 makes a pin-name list for thedesignated region. The compiled pin-name list is memorized and reservedin the pin-list storage section 26. In the circuit-informationextraction section 24, the circuit information with regard to retrievalitems of the retrieval condition is extracted for each pin-name list,based on the pin-name list, the circuit information and the retrievalcondition and circuit information for each pin list is generated. Thegenerated circuit information for each pin list is memorized andreserved in the circuit-information for each pin-list storage section27.

Based on the pin-name list stored in the pin-list storage section 26 andcircuit information for each pin list stored in the circuit-informationfor each pin-list storage section 27, the path-list generation section14 makes a path list for new paths. The path-list generation section 14is not required to make a path list by reading required circuitinformation from a vast amount of circuit information recorded in thecircuit-information storage section 13. The amount of the circuitinformation for each pin list is far smaller than that of the circuitinformation recorded in the circuit-information storage section 13.Moreover, the amount of information can be much more reduced because thecircuit information is stored with regard to only the pin-name list.

When a path-list of new paths cannot be generated so as to fail toextract the new path, the path-list generation section 14 set a failedextraction flag. The circuit-information changing section 23 detects thefailed-extraction flag to relieve the retrieval condition. The path-listgeneration section 14 makes a path-list of new paths, based on therelieved retrieval condition, and extraction of a new path is continued.

A compiled path-list is for paths which pass a region designated by thechip-region designation section 20. The test-vector generation section16 generates a test vector for the path list. The region designated bythe test vector can be tested. When the test-vector generation section16 fails in generation of the test vector, the circuit-informationchanging section 23 relieved the retrieval condition. The test-vectorgeneration section 16 continues the generation of the test vector, basedon the relieved retrieval condition. That is, retrieval conditions forgeneration of a path list at STEP S14 after STEPs S17, S18, S13 are notrelieved in some cases, depending on retrieval conditions which havebeen relieved at STEP S22 in FIG. 6. Only retrieval conditions forgeneration of test vectors at STEP S16 are relieved in some cases. Aflow chart in which the processing proceeds to STEP S16 after NOdecision is obtained at STEP S18 is configured when the retrievalconditions only for the above generation of test vector is relieved.

Thus, a test vector which is finally generated can have higher qualityin the apparatus for generating a test vector, because a region to whicha path for which the operator desires to form a test vector isdesignated, a new path can be repeatedly retrieved while changing theretrieval condition for a path list in the designated region, and a newtest vector can be repeatedly formed while changing the generationcondition of test vectors for the extracted path.

Furthermore, an operator of the apparatus for generating a test vectorcan input a desired region into the chip-region designation section 20,responding to a request of the section 20 when a region to which a pathfor which a test vector is desired to be formed is designated. By theinput of the desired region, the chip-region designation section 20,which designates a region the operator desires as a region in which apath for a test vector is made. Thus, the operator can adjust thequality of the test vector.

(Variant 5 of the First Embodiment)

An apparatus for generating a test vector according to a fifth variantof the first embodiment has a configuration, as shown in FIG. 9. Anapparatus for generating a test vector the fourth variant of the firstembodiment shown in FIG. 8. The fifth variant further includes: apath-circuit-information making section 191; a path-circuit-informationstorage section 192; a highlighted-path selection section 193; ahighlighted-path information storage section 194; and a delimiter-valuedesignation section 195.

The path-circuit-information making section 191 makes circuitinformation for each retrieval item on a path which covers regions aredesignated by the chip-region designation section 20. The circuitinformation is made based on the circuit information, which has beenextracted in the circuit-information extraction section 24, for each pinlist according to the retrieval items.

The delimiter-value designation section 195 sets a delimiter valuewithin or beyond a setting range of retrieval items for the retrievalcondition. If the setting range is divided into a plurality of zoneswith the delimiter value, generating priorities can be assigned to pathsat generation of a test vector. If the delimiter value is set beyond thesetting range, the number of paths is increased by extending the settingrange to the delimiter value to satisfy the ending condition when a pathsatisfying the setting range does not satisfy an ending condition. Here,the delimiter-value designation section 195 is preferably provided inthe retrieval-condition designation section 11 because the delimitervalue is set with regard to items selected from retrieval items for theretrieval condition.

The highlighted-path selection section 193 compares the circuitinformation on paths according to each retrieval item with the delimitervalue. The paths are distinguishably displayed and are superposed on ascreen image of the semiconductor integrated circuit for each zone,which is divided by the delimiter value, and to which the circuitinformation on paths belongs, according to each retrieval item.

The path-list generation section 14 generates a path-list. The generatedpath-list is stored in the path-list storage section 15. The circuitinformation on paths in the path list is made or compiled in thecircuit-information making section 191. The made circuit information onthe paths is stored in the path-circuit-information storage section 192.

The highlighted-path selection section 193 selects a path, which has thevalue of the circuit information on the path which exceeds the delimitervalue which the delimiter-value designation section 195 has set, fromthe paths stored in the path-circuit-information storage section 192.With regard to a retrieval item for which the delimiter value isprovided, the larger the value of a path is, the stronger the tendencyto extract the path. Accordingly, exceeding the set delimiter value is astandard for extracting the path. The highlighted-path selection section193 makes a list of paths for which the screen images are superposed onthe screen image of the semiconductor integrated circuit whilehighlighting the screen images of the paths. The list of paths for whichthe highlighting is executed is stored in the highlighted-pathinformation storage section 194.

In the chip-region designation section 20, paths in the path-list storedin the highlighted-path information storage section 194 are superposedon the screen image of the semiconductor integrated circuit and arehighlighted. A method in which the line width of the line segment of ahighlighted path is more thicker than that of a non-highlighted path, oranother path by which the color of the line segment of a path ischanged, depending on a path to be highlighted or a path not to behighlighted can be used as the highlighting method.

In the above-described test-vector generating method, the chip-regiondesignation section 20 can select a region of a path, thedelimiter-value designation section 195 sets a delimiter value forhighlighting of a retrieval item as the retrieval condition, thehighlighted-path selection section 193 selects a path to be highlightedbased on the delimiter value, and the chip-region designation section 20highlights the selected path. Accordingly, an operator can confirmwhether a highlighted path is arranged in a selected region or not. Bythe above confirmation the operator can effectively select a chip-regionagain so that a set of the test vectors finally generated becomes higherquality test vectors. For example, the operator can select a region inwhich a highlighted path is not arranged.

(Second Embodiment)

A fault analysis apparatus of a semiconductor integrated circuitaccording to the second embodiment executes operations corresponding toSTEPs S6 through S8 in FIG. 1 according to the first embodiment. Thefault analysis apparatus executes a test of a processed semiconductorintegrated circuit and a fault analysis of a semiconductor integratedcircuit as required. In the fault analysis apparatus, a test is executedfor analysis of a path delay fault of the semiconductor integratedcircuit, a fail path is analyzed, and lists of cell names and pin namesare generated. The fault analysis apparatus generates a path-list of adifferent path which has a common part of the fail path. Furthermore,the fault analysis apparatus generates a test vector for the path listof the different path to conduct testing. It is decided that a fault iscaused on the common part of the fail path when a further path fails inthe testing. As described above, a fault point can be located bygenerating a test vector for a different path which has a part of thefail path in common by repeating the testing. In such a fault analysis,the fault analysis apparatus designates a retrieval condition for a pathat generation of a path list and a generation ending condition atgeneration a test vector, in a similar way to that of the apparatus forgenerating a test vector according to the first embodiment. Thereby, atest-vector generating method for analysis of a path delay fault ishighly automated and the quality of the generated test vector foranalysis can be improved compared to a predetermined test vector.

A fault analysis apparatus of a semiconductor integrated circuitaccording to the second embodiment includes as shown in FIG. 10: a testexecution section 41; a fail-data storage section 42; a cell-listgeneration section 43; a cell-list storage section 44; a path-listgeneration section 34; a path-list storage section 35; test-vectorgeneration section 36; test-vector storage section 37; aretrieval-condition designation section 31; an ending-conditiondesignation section 32; a circuit-information storage section 33; anending-condition judgment section 39; a vector-generation-informationstorage section 38; an input section 204; and an output section 206.

The test execution section 41 executes a test for judging whether adelay fault is caused on a path in the processed semiconductorintegrated circuit. A test vector 1 in FIG. 1 can be used in the test.The test vector 1 is stored in a test-vector storage section 17 in FIG.2. The fail-data storage section 42 stores a result for a delay faulttest. Especially, a distinguishable display number of a fail path, onwhich a delay fault is caused, is stored.

The cell-list generation section 43 generates a cell list of cellsforming the fail path, based on the result of a delay fault test and thesemiconductor integrated circuit stored in the circuit-informationstorage section 33. The cell-list storage section 44 stores the celllist of cells forming the generated fail path.

The retrieval-condition designation section 31 designates a retrievalcondition which retrieves a path for searching a fault cell having apart of the fail path.

The path-list generation section 34 retrieves the path for searching afault cell, based on the designated retrieval condition, and generates apath list for fault-cell searching, wherein cells forming the retrievedpath for fault-cell searching are arranged in the order by which asignal can be transmitted. The path-list storage section 35 stores thegenerated path list for fault-cell searching.

The test-vector generation section 36 generates a test vector forfault-cell searching, based on the circuit information in thecircuit-information storage section 33, for each path in the path listfor fault-cell searching. The test-vector storage section 37 stores thetest vector for fault-cell searching. The vector-generation-informationstorage section 38 stores a generation state of the test vector asvector-generation information.

The ending-condition designation section 32 designates an endingcondition which ends the generation of the test vector. Here, the endingcondition to be designated may be of a fixed type or of a variable type.The ending-condition judgment section 39 stops generation of thepath-list when the vector-generation information satisfys the endingcondition.

The input section 204 and the output section 206 exchange data betweenthe fault analysis apparatus of the semiconductor integrated circuit,and the external apparatus or the operator.

(Fault Analysis Method for a Semiconductor Integrated Circuit)

A fault analysis method of a semiconductor integrated circuit accordingto the second embodiment can be executed by a computer. In the faultanalysis method of a semiconductor integrated circuit according to thesecond embodiment, a test for a delay fault in the semiconductorintegrated circuit is executed by the test execution section 41 at STEPS31, as shown in FIG. 11. A specific path on a logic circuit of a usercircuit in the semiconductor integrated circuit is activated. A testvector for a delay fault test on the path is used in order to activatethe path. STEP S31 corresponds to STEP S6 in FIG. 1. Subsequently, it isjudged at STEP S7 in the second embodiment whether the fault analysis isrequired or not, depending on the presence of a fail path in the test.When the fail path is not generated, the processing proceeds to STEP S9in the second embodiment to stop the processing of the semiconductorintegrated circuit. When the fail path is generated, the processingproceeds to STEP S8 as the second embodiment for fault analysis. STEP S8in the second embodiment includes STEPS S32 through S43 in FIG. 11,which will be explained as follows.

When a fail path is generated at the test, the test execution section 41makes or compiles fail data including a distinguishable display numberof the fail path as the test result at STEP S32. The fail-data storagesection 42 stores the made or compiled fail data. The fail data is thejudgment results of the tests for each path, test numbers, measureddelay time and the like.

Then, circuit information on the semiconductor integrated circuit isinput from the circuit-information storage section 33 to the cell-listgeneration section 43 at STEP S33. The circuit information to be inputmay be a netlist in which information on cell connection is described,or layout information on a circuit of placing and routing of layout ofthe cells when a more details placing and routing of layout of the cellsis a retrieval condition for path retrieval.

The cell-list generation section 43 generates at STEP S34 a cell list ofcells forming the fail path, based on the fail data and the circuitinformation. The generated cell list is stored in the cell-list storagesection 44.

The retrieval-condition designation section 31 designates at STEP S35 aretrieval condition, based on which, a path sharing a part of the failpath is retrieved, for fault-cell searching. The total number of stepsand the total wiring lengths on the path, the number of contacts andvias, designation of a layer to which wiring and the vias belong, andthe like can be listed as a retrieval condition for fault-cell searchingin a similar manner to that of STEP S13 in FIG. 3. Preferably, theretrieval range corresponding to the retrieval item is different fromthat of STEP S13 in FIG. 13. Moreover, a high quality test vector can begenerated while reducing the number of test vectors by designating anumber of steps of the path shared with the target fail path for thefault analysis as the retrieval condition.

At STEP S36, the ending-condition designation section 32 designates theending condition for fault-cell searching to end generation of a testvector. A condition that a number of test vectors which have succeededin generation is equal to or larger than a predetermined number, or atrial of generation of test vectors for all the paths to be tested isassumed to be as an ending condition for fault-cell searching in asimilar manner to that of STEP S12 in FIG. 3. Thus, it is easier tonarrow down a fault point, since almost all the parts of the fail pathare shared by generation of vectors for all the path-lists. The endingcondition for fault-cell searching can be set in such a way that thecell causing the failure can be located in the fail path by a set oftest vectors satisfying the condition. Moreover, the ending conditioncan be designated, considering to what degree the detailed analysis isexecuted for a test vector which is generated for fault analysis of thesemiconductor integrated circuit. Here, the executing order of STEPsS35, S36 may be arbitrary, or the above STEPs may be simultaneouslyexecuted.

AT STEP S37, the path-list generation section 34 extracts cells, basedon the cell list of the fail path and the retrieval condition; performstiming analysis of the path circuit according to the retrieval conditionafter designating a cell name as a distinguishable display number of thecell; and makes a path list for fault-cell searching for a path, whichsatisfys the retrieval condition. The path-list for fault-cell searchingmade by the path-list storage section 35 is stored. It is judged in thepath-list generation section 34 at STEP S38 whether a path forfault-cell searching, which satisfys the retrieval condition forfault-cell searching is extracted or not. When extracted, the processingproceeds to STEP S39. When not extracted, the processing returns to STEPS35 and the retrieval condition is adjusted again. When a path existsfor fault-cell searching which has already been extracted and a testvector for fault-cell searching with regard to the path is generatedafter a loop from STEP S35 through STEP S41, wherein the processingproceeds into the loop in the case of NO at STEP S41, then theprocessing proceeds to STEP S42.

The path-list for fault-cell searching and the circuit information onthe semiconductor integrated circuit stored in the circuit-informationstorage section 33 are input to the test-vector generation section 36,at STEP S39 and a test vector for fault-cell searching is generated,wherein the test vector can detect a delay fault in each path includedin the path-list for fault-cell searching. The circuit information mayhave a detail level and description format different from that of thecircuit information used in generate the path-list at STEP S37. When thetest vector is successfully generated for fault-cell searching, thetest-vector generation section 36 stores the test vector in thetest-vector storage section 37. Moreover, the section 36 stores adistinguishable display number of a path for fault-cell searching andvector-generation information, whether the test vector is successfullygenerated or not, in the vector-generation-information storage section38.

The ending-condition judgment section 39 judges at STEP S40 whether thevector-generation information satisfys the ending condition forfault-cell searching.

When it is decided at STEP S41 in the ending-condition judgment section39 that the vector-generation information is in accordance with theending condition for fault-cell searching, the processing proceeds toSTEP S42 to stop generation of the test vector.

When it is decided at STEP S41 in the ending-condition judgment section39 that the information is not in accordance with the ending conditionfor fault-cell searching, the processing returns to STEP S35. Theretrieval-condition designation section 31 updates the retrievalcondition to a new condition for fault-cell searching at STEP S35. A newpath for fault-cell searching, which satisfys the updated retrievalcondition for fault-cell searching, is retrieved and a path-list and atest vector for fault-cell searching are generated by processing betweenSTEP S35 and STEP S41. The loop is ended when a new path in accordancewith the retrieval condition for fault-cell searching is not retrieved,or when the vector-generation information is in accordance with theending condition for fault-cell searching, and the processing proceedsto STEP S42.

At STEP S42, the test-vector generation section 36 extracts a finalvector-generation information and outputs the final vector-generationinformation to the external memory. At STEP S43, the test-vectorgeneration section 36 outputs the generated test vector for fault-cellsearching to the external memory.

Thus, a generating method of a test-vector for analysis of a delay faultpath can be highly automated and the quality of a generated test vectorfor fault-cell searching can be improved to a higher and more uniformtest vector by generating the test vector for a path for fault-cellsearching, based on the cell list for the fail path, the retrievalcondition and the ending condition. Moreover, the period which has beenrequired for fault analysis has been from several weeks through severalmonths in manpower, but the period according to the invention is reducedto several days through several weeks.

(Variant 1 of the Second Embodiment)

As shown in FIG. 12, a fault analysis apparatus of a semiconductorintegrated circuit according to a first variant of the second embodimentfurther includes a chip-region designation section 50 in addition tocomponents of the fault analysis apparatus according to the secondembodiment shown in FIG. 10.

The chip-region designation section 50 displays a line segment of a failpath on the screen image of the semiconductor integrated circuitincluding the screen image of the fail path so that the line segment isalong the screen image of the path. The line segment of the fail pathcan be distinguished from the screen image of the semiconductorintegrated circuit. Preferably, the line segment of the fail path ishighlighted.

The chip-region designation section 50 displays a line segment of a pathfor fault-cell searching so that the segment is along the screen imageof the path, which includes a part of the fail path, for fault-cellsearching. The line segment of a path for fault-cell searching can bedistinguished from the screen images of the semiconductor integratedcircuit and the fail path, and the line segment of the fail path.Preferably, the line segment of a path for fault-cell searching ishighlighted. Especially, it is preferable to change colors of the linesegments in order to distinguish the line segment of the fail path fromthat of the path for fault-cell searching. Other methods, such as amethod for changing the widths of the line segments and a method forusing a solid line and a dotted line for the distinction between thesegments, can be used as a distinguishing method for the segments.

The fault-analysis method of the semiconductor integrated circuit, usingthe above fault-analysis apparatus basically has the same configurationas that of FIG. 11. Furthermore, the chip-region designation section 50reads the placing and routing of layout information of the semiconductorintegrated circuit from the circuit-information storage section 33 anddisplays the chip region of the semiconductor integrated circuit at STEPS40. Then, the cell list of the fail path from the cell-list storagesection 44, the list of paths newly retrieved from the path-list storagesection 35 and the vector-generation information from thevector-generation information storage section 38 are input to thechip-region designation section 50. Then, images of the fail path and apath for which a new test vector is generated are displayed on the imageof the chip region.

The chip-region designation section 50 requests an operator, using animage display, to update a retrieval condition for a path to be newlyretrieved when there is not a sufficient test vector for fault analysis.Responding to the request, the operator inputs an intent for updatingthe retrieval condition or a concrete retrieval condition to the section50. The section 50 outputs the input retrieval condition and the like tothe retrieval-condition designation section 31. The retrieval-conditiondesignation section 31 updates the retrieval condition to the input oneand the like. Accordingly, a test vector finally generated can beadjusted in such a way that the vector becomes the best available as avector for fault analysis.

The chip-region designation section 50 checks the degree of overlap ofthe fail path with the path for which a new test vector is generated,using an image display. The chip-region designation section 50 requeststhe retrieval-condition designation section 31 to update the retrievalcondition to a new condition for retrieval of a path passing a cell whenthere is a cell which cannot share a new path, in the fail path. Theretrieval-condition designation section 31 updates the retrievalcondition to a retrieval condition by which a path passing the cell canbe retrieved.

(Variant 2 of the Second Embodiment)

As shown in FIG. 13, a fault analysis apparatus of a semiconductorintegrated circuit according to a second variant of the secondembodiment further includes a pin-coordinate storage section 51 inaddition to components of the fault analysis apparatus according to thesecond embodiment shown in FIG. 10. Only parts related with the additionof the pin-coordinate storage section 51 are shown in FIG. 13.

In the cell-list generation section 43, the placing and routing oflayout information of a cell in the semiconductor integrated circuit isread from the circuit-information storage section 33 and pin-coordinateinformation of the input/output pin of a cell forming the fail path isgenerated, based on the placing and routing of layout information of thecell. The pin-coordinate storage section 51 stores pin-coordinateinformation. In the pin-coordinate information, an x-coordinate and ay-coordinate of a pin of the cell are associated with a pin name, whichis written in a netlist, of the cell in such a way that both coordinatescan be retrieved. The pin-coordinate information includes a data regionwhich can memorize the pin name and another data region which canmemorize x- and y-coordinates of the pin.

In the fault analysis technique of the semiconductor integrated circuit,a test method by which electron beams are irradiated on a chip foranalysis of electric potential is simultaneously used in some cases. Inthe above test method, the pin-coordinate information of theinput/output pin of the cell is indispensable in order to irradiateelectron beams on the input/output pin of the cell. According to theabove test method, the pin-coordinate information is automaticallygenerated as fail-path information to reduce time required for faultanalysis.

(Variant 3 of the Second Embodiment)

In a fault analysis apparatus of a semiconductor integrated circuitaccording to a third variant of the second embodiment, fail data from afail-data storage section 42 is further input to a chip-regiondesignation section 50 according to the first variant of the secondembodiment of FIG. 12, as shown in FIG. 14. A retrieval condition andthe like are output from the chip-region designation section 50 to aretrieval-condition designation section 31 and an ending condition andthe like are output to an ending-condition designation section 32. Onthe other hand, a cell list is not output from a cell-list storagesection 44 to the chip-region designation section 50.

By the above differences, the chip-region designation section 50 readsthe logic circuit information of the semiconductor integrated circuitfrom a circuit-information storage section 33, and an image of a logiccircuit part, for which a test vector for a path test is desired to bemade, of a user logic having the peculiar specifications of a user on achip is displayed. Moreover, the chip-region designation section 50designates a method by which the logic circuit part for which the testvector is desired is divided into regions, divides the part into theregions, and generates divided-region information including shapes,sizes and arranged positions of the regions. The chip-region designationsection 50 displays the images of the divided regions on the image ofthe logic circuit part in a superposed manner, based on thedivided-region information. The region dividing method has aconfiguration in which the logic circuit part may be equally dividedinto regions by designating numbers of partitions in the vertical andhorizontal directions, respectively, or, an operator may designate aregion on a display screen.

A successful path, i.e., a no fail path and fail data on a fail path areinput from the fail-data storage section 42 to the chip-regiondesignation section 50, images of the successful path and a physicalposition of the fail path on the chip are displayed. The fail path andthe successful path are displayed so that both paths can bedistinguished from each other. By display of the successful and failpaths, an operator can confirm a ratio between the successful paths andthe fail paths in each region and a distribution bias between thesuccessful paths and the fail paths in all the chip.

The chip-region designation section 50 sets a coverage condition for thefail paths, based on the coverage of the fail paths, which is obtainedby replacing the generated path by the fail path, and coverage regionssatisfying the coverage condition and non-satisfying regions aredisplayed so as to be distinguished from each other. The above displaymay be achieved by changing colors for images. A condition that a numberof fail paths passing a region is equal to or larger than apredetermined value can be applied for a coverage condition for the failpaths.

In the retrieval-condition designation section 31, a condition that aregion which the fail path covers is covered by a path for fault-cellsearch is newly set as a retrieval condition. Alternatively, thechip-region designation section 50 requests an operator to displayingregions, which the fail paths cover, on the chip to specify and input aregion which is desired to be covered with a path for fault-cellsearching. The operator inputs regions to be covered into thechip-region designation section 50, responding to the above request. Thechip-region designation section 50 outputs the operator input region tothe retrieval-condition designation section 31. In theretrieval-condition designation section 31, a condition that a regionwhich an operator desires to cover is covered is newly set as aretrieval condition.

Based on the new retrieval conditions, the path-list generation section34 retrieves a path for fault-cell searching and generates a path-listof the path. The test-vector generation section 36 generates a testvector for the generated path-list. The test-vector generation section36 outputs vector-generation information to the vector-generationinformation storage section 38 for storage when the test vector issuccessfully generated. The chip-region designation section 50 alsodisplays the image of the new path for fault-cell search, based on thevector-generation information.

The chip-region designation section 50 can designate not only aretrieval condition for designating a region, but priorities forgeneration of a path list as a retrieval condition. Furthermore, thechip-region designation section 50 can designate priorities forgeneration of a test vector as a retrieval condition. Furthermore, thedesignation of a region by the chip-region designation section 50 may beperformed at STEP S35 and S36 in the loop after a test vector isgenerated at STEP S40 in FIG. 11 for every loop or every predeterminednumber of loops.

Thus, situations of paths which succeed in the test, and of failedpaths, or situations of test-vector generation during generation ofpaths for fault-cell searching can be displayed. The followingpriorities in the retrieval condition for path lists and in the endingcondition for test vectors can be automatically designated by anoperator, based on the above display. Thereby, the set of test vectorsfinally generated can provide a highly accurate fault-analysis.

EXAMPLE Example 1 of the First Embodiment

In a test-vector generating method according to an example 1 of thefirst embodiment, circuit information is input from thecircuit-information storage section 13 to the path-list generationsection 14 at STEP S11, as shown in FIG. 3.

Then, an ending condition shown in FIG. 16 is generated in theending-condition designation section 12 at STEP S12. The endingcondition has an ending-condition-item data region 54 and anend-condition-range data region 55 so that a computer can write and readdata. The end-condition-item data region 54 has a number of test vectorsand a number of logic elements which the test vectors pass as item data.The end-condition-range data region 55 has range data associated so thatretrieval using each item data can be executed. The number of testvectors and the number of logic elements which the test vectors pass isin a range of 20 or more and the number of gates is 200 or more.

At STEP S13, a retrieval condition for retrieval is generated in theretrieval-condition designation section 11 as shown in FIG. 15. Theretrieval condition has a retrieval-condition-item data region 52 and aretrieval-condition-range data region 53 so that a computer can writeand read data. The retrieval-condition-item data region 52 includes asitem data a total number of steps for the path, a number of logicelements which the test vectors pass, and a number of vias. Theretrieval-condition-range data region 53 has range data associated withitem data, so that the range data can be retrieved using each item data.The total number of steps for the path is associated with a range of tensteps or more. The number of logic elements which the test vectors passthrough is associated with a range of 300 gates or more. And the numberof vias is associated with a range of 1000 pieces or more.

Then, a path-list of paths as shown in FIG. 17 is generated in thepath-list generation section 14 at STEP S14. The path-list has apath-list data region 56 so that a computer can write and read data. Thepath-list data region 56 has a distinguishable display number of path 1for a path as leading-line data: Path 1-1. The path-list data region 56has a distinguishable display number of GFD1EX2 for a cell as acell-line data: Cell 1-1. The path-list data region 56 has adistinguishable display number of (GNR2X1) for a cell as cell-line data:Cell 1-2. The cell-line data: Cell 1-2 is arranged below the cell-linedata: Cell 1-1. Similarly, the path-list data region 56 has adistinguishable display number of (GIVX1) for a cell as cell-line data:Cell 1-3. The cell-line data: Cell 1-3 is arranged below the cell-linedata: Cell 1-2. Similarly, the path-list data region 56 hasdistinguishable display numbers for cells as cell-line data: Cell 1-4through 1-19. The distinguishable displays as cell-line data: Cell 1-4through 1-19 are sequentially arranged from the Cell 1-4. In theconfiguration of the path-list data region 56, nineteen steps of theCell 1-1 through Cell 1-19 are sequentially connected to each other inan ascending order from the Cell 1-1 to form the path of path 1. Theabove nineteen steps satisfy the retrieval condition that the totalnumber of steps for the path in FIG. 15 is ten steps or more.

It is judged at STEP S15 whether a new path-list of paths is extracted.Since the path-list for a new path of path 1 has been generated, theprocessing proceeds to STEP S16.

At STEP S16, the test-vector generation section 16 generates testvectors and test-vector generation information of whether the testvectors have succeeded in generation for each path as shown in FIG. 18is generated. The test-vector generation information has an item dataregion 57 for test vector generation information and a situation dataregion 58 for test-vector generation information so that a computer canwrite and read data. The item data region 57 includes as item data: anumber of input paths; a number of generated test vectors; numbers ofpaths which have succeeded in generation of test vectors; numbers ofpaths which have failed in generation of test vectors; and names of thetest vectors. The situation data region 58 has situation data associatedwith item data so that the situation data can be retrieved using eachitem data. The number of input paths is associated with a number of ten.The number of generated test vectors is associated with a number offive. The distinguishable displays (numbers) of paths successful ingeneration of test vectors are associated with numbers of path1, path4,path5, path7 and path8. The numbers of paths which failed in generationof test vectors are associated with numbers of path2, path3, path6,path9, and path10. And the names of test vectors are associated withnames of pat 1, pat4, pat5, pat7, and pat8.

It is judged at STEP S17 in the ending-condition judgment section 19whether the test-vector generation information satisfys the endingcondition. While the number of generated test vectors for test-vectorgeneration information in FIG. 18 is five, the number of test vectorsfor the ending condition in FIG. 16 is 20 or more. Accordingly, thetest-vector generation information does not satisfy the endingcondition. At STEP S18, the processing returns to STEP S13.

At STEP S13, a new retrieval condition is designated for updating. AtSTEP S14, a new path is retrieved and a path-list for the path isgenerated again. At STEP S15, it is judged whether a path-list for thenew path is generated. When the path-list for the new path is generated,the processing proceeds to STEPs S16, S17, S18, and, finally, to STEPS19. Even when the path-list for the new path is not generated, theprocessing proceeds to STEP S19. At STEP S19, final test-vectorgeneration information is output to the external memory. Furthermore, afinal test vector is output to the external memory at STEP S20.

Thus, the test-vector generating method can be highly automatedaccording to the apparatus for generating a test vector, because a testvector for a path can be generated by executing the test-vectorgenerating method, using the retrieval condition and the endingcondition.

Example 2 of the First Embodiment

A second example of the first embodiment is a case of an apparatus forgenerating a test vector similar to the apparatus for generating a testvector shown in FIG. 4 describing the first variation of the firstembodiment. The apparatus for generating a test vector includes achip-region designation section 20, as shown in FIG. 4. STEP S13 of thetest-vector generating method according to the first example of thefirst embodiment shown in FIG. 3 is expanded and changed into a step ofa test-vector generating method according to the second example of thefirst embodiment.

The chip-region designation section 20 generates a screen image 61 ofthe entire chip area of the semiconductor integrated circuit, based onlogic-circuit information of a semiconductor integrated circuit, asshown in FIG. 19. The screen image 61 is displayed on a display sectionin the section 20 as an image which an operator can recognize.

Then, the chip-region designation section 20 generates regions 69through 80 which divide the screen image 61. The chip-region designationsection 20 decides to divide the screen image 61 so that the image isequally separated to three sections in the vertical direction and foursections in the horizontal direction. The chip-region designationsection 20 generates display-image division information includingpositions for images of line segments which divide the screen image 61.The section 20 divides the screen image 61 into 69 through 80 sectionsof regions by superposing the images of line segments, which divide thescreen image 61 on the screen image 61, based on the display-imagedivision information. There are provided 62 through 66 sections ofdisplay regions for electrode pads on the peripheral part of the screenimage 61. For example, a display 67 of a path is provided between thedisplays 63 and 66 for the electrode pads. The display 67 of the pathpasses through regions 71 and 73 through 75. A display 68 of a path isprovided between the displays 64 and 65 of the electrode pad. Thedisplay 68 of the path passes through only the region 69.

The screen image 61 of the entire chip area of the semiconductorintegrated circuit shown in FIG. 19 is equally divided into regions 69through 80. A case in which an equally-dividing method is not suitable,and a dividing method for such case will be explained below. Thechip-region designation section 20 generates an image 81 of the entirechip area of the semiconductor integrated circuit, based on the logiccircuit information of the semiconductor integrated circuit, anddisplays the image 81 on the display section as shown in FIG. 20. Theimage 81 of the entire chip area includes screen regions 82 through 86of mega cells. The image 81 excluding screen regions 82 through 86 ofthe mega cells includes screen regions 93, 94 of large-scale logiccircuits. Mega cells 82 through 86 are circuit blocks which aregenerally built in, and testing can be executed for each mega cell 82through 86 which has been already provided with a path 108 to be testedand a test vector for the path by timing analysis during processing forgeneral use. The large-scale logic circuits 93, 94 are so-called userlogic designed for the chip 81 and requires testing for a delay fault. Apath for the large-scale logic circuits 93, 94 is retrieved to generatea test vector.

The large-scale logic circuit 93 includes: a flip-flop register 100 forscanning; and electrode pads 87, 88 connected to the register 100through wiring 109. Similarly, the circuit 93 includes: a flip-flopregisters 98, 99 for scanning; and electrode pads 89, 90 connected tothe registers 98, 99 through wiring 110. A path 101 is provided betweenthe registers 99, 100. A signal cannot be input or output directly to orfrom the registers 99, 100, different from the electrode pads 87 through90. Accordingly, a preparation vector, a system-clock vector, and adetection vector are used as a test vector in order to test the path101. The preparation vector is input from the electrode pads 87, 89 toset initial logic for the registers 99, 100 and the like before thetesting. The system clock vector is input from the electrode pads 87,89, 97, and the like to activate the path 101. The detection vector isan expectation value of the testing and is compared with an outputvector from the electrode pad 88, caused by an output signal from theactivated path 101.

Similarly, the large-scale logic circuit 94 includes: registers 103,105, 106, 111 and electrode pads 91, 92 connected to the above registers103, 105, 106, 111 by wiring. The path 104 is provided between theelectrode pad 102 and the register 103. A path 107 is provided betweenthe registers 105, 106. A test vector is generated for input or outputof a signal to or from the registers 103, 105, 106.

When the large-scale logic circuits 93, 94 are equally divided intoregions in a similar manner to that of FIG. 19, large regions 71, 74,75, 78, 79, 80, and small regions 69, 70, 72, 73, 76, 77 are formed asshown in FIG. 21. Especially, the existence of the small regions 69, 76makes it difficult to control the path for uniformity on the chip.

Therefore, the large-scale logic circuits 93, 94 are divided intoregions 116 through 128, as shown in FIG. 22, and non-uniformity amongthe areas of the regions is relieved when the chip-region designationsection 20 directly designates each of the regions.

The chip-region designation section 20 displays the screen images of thelarge-scale logic circuit 93, 94 of the semiconductor integratedcircuit. Using the screen displays, an operator of the apparatus forgenerating a test vector is requested to divide the screen images of thelarge-scale logic circuits 93, 94 into regions, based on the screenimage of the semiconductor integrated circuit and to designate a dividedregion. The operator selects the screen image of the large-scale logiccircuit 94, responding to the request of the chip-region designationsection 20 and inputs an intent to divide the screen image of thecircuit 94 into five regions 116 through 120 to the section 20 withequal area as shown in FIG. 22. Moreover, the operator selects thescreen image of the large-scale logic circuit 93, responding to therequest of the chip-region designation section 20 and inputs an intentto designate a part of the screen image of the circuit 93, and to dividethe part of the screen image into three equal area regions 121 through123; an intent to designate another part of the screen image of thecircuit 93, and to divide the part of the screen image into four equalarea regions 124 through 127; and an intent to designate a final part ofthe screen image of the circuit 93, and to set the part of the screenimage as the region 128 to the section 20. By touching a screen image ofa region displayed on a touch panel, the operator inputs theabove-described intentions to generate regions after dividing. Theretrieval-condition designation section 11 divides the large-scale logiccircuits 93, 94, and generate regions 116 through 128, based on theintents to generate regions after dividing. Thereby, regions 116 through128 with approximately uniform circuit area can be generated, even ifthe semiconductor integrated circuit 81 has mega cells. Hereinafter,explanation will be made, assuming for easy explanation that the circuitarea is equally divided into regions in the vertical and horizontaldirections, as shown in FIG. 19.

As shown in FIG. 23, screen images of paths 133, 134 which have alreadysucceeded in generation of a test vector are superposed and displayed,by the chip-region designation section 20, on the screen image 61 of thesemiconductor integrated circuit which has been divided into regions 69through 80. The screen images of the paths 133, 134 can be generated,using a path list 131 and circuit information 132. The screen image ofthe path 133 is provided so that the image is superposed on the region69, 73, 74, and the screen image of the path 134 is provided so that theimage is superposed on the region 70, 74, 77, 78.

The chip-region designation section 20 generates definition, as shown inFIG. 24, of coverage (coverage condition) of the regions 69 through 80by the paths, 133, 134. The definition of the coverage has acoverage-definition-item-data region 141 and a range data region 142.The item data region 141 includes as item data; the number of pathspassing through the region and the total length of wiring which isconnected to the path in each region. The range data region 142 hasrange data associated with item data so that the range data can beretrieved using each item data. The total number of paths which passthrough the region is associated with a range of three or more. And thetotal wiring length connected to paths are associated with a range of 2mm or more.

The chip-region designation section 20 authorizes, after checking, thatthe total wiring length connected to a path with regions 69, 70, 73, 74,77, 78 is 2 mm or more and the regions 69, 70, 73, 74, 77, 78 aredistinguishably hatched for coverage as shown in FIG. 27. Since thenumber of the covered regions 69, 70, 73, 74, 77, 78 is six and thetotal number is twelve, a ratio between both numbers, that is, thecoverage rate is 50%. Here, the displayed path 147 is a path which hasfailed in generation of a test vector.

An ending-condition designation section 12 generates ending-conditionsshown in FIG. 26. The ending conditions has an item-data region 145 anda range-data region 146. The item-data region 145 includes, as itemdata: a coverage rate; the number of test vectors; and the number oflogic elements which the test vectors pass. The range-data region 146includes range data associated with item data so that the range data canbe retrieved using each item data. The coverage rate is associated witha range of 70% or more. The number of test vectors is associated with arange of 30 vectors or more. And, the number of logic elements which thetest vectors passes is associated with a range of 300 gates or more.

The ending-condition judgment section 19 judges that the coverage rateis 50% and does not satisfy the condition of a range of 70% or more.

Accordingly, the chip-region designation section 20 generates aretrieval condition shown in FIG. 25. The retrieval condition has aretrieval-condition-item data region 143 and a range data region 144.The item data region 143 has a coverage rate, a total number of stepsfor the path, and a number of logic elements and that of vias throughwhich the test vectors pass, as item data. The range-data region 144includes range data associated with item data so that the range data canbe retrieved using each item data. The coverage rate is associated witha range of 70% or more. The total number of steps for the path isassociated with a range of 7 steps or more. The number of logic elementswhich the test vectors pass is associated with a range of 200 gates ormore. And the number of vias is associated with a range 500 pieces ormore.

The chip-region designation section 20 requests an operator of theapparatus for generating a test vector to designate one of dividedregions 69 through 80 based on the screen image 61 of the semiconductorintegrated circuit, using a hatched screen image 61 shown in FIG. 27.

The operator designates a region 80, which a path is desired to bearranged, by seeing the hatched screen image 61, as shown in FIG. 28,responding to the request from the chip-region designation section 20,and inputs an intent to designate the region 80 to the section 20. Theoperator is required only to select the region 80 which the path isdesired to be arranged from among uncovered regions 71, 72, 75, 76, 79,80.

The retrieval-condition designation section 11 recreates a retrievalcondition by adding a retrieval condition on which a path arranged inthe designated region 80 can be retrieved to the retrieval condition inFIG. 25, based on the intent to designate the region 80. The path-listgeneration section 14 generates a path list which satisfys the recreatedretrieval condition. And, the test-vector generation section 16 displaysa path 148 shown in FIG. 29 after success in generation of a testvector.

The chip-region designation section 20 highlights a path 148, as shownin FIG. 29, in such a way that the path 148 can be distinguished fromthe path 147. It is judged in the chip-region designation section 20whether the uncovered regions 75, 79, 80 which have not yet been hatchedand through which the path 148 passes satisfys the definition of thecoverage in FIG. 24. Since the total wiring length connected to the pathis 2 mm or more with regard to the regions 75, 79, 80, the regions 75,79, 80 are hatched as a covered region. The number of covered regions69, 70, 73 through 75, 77 through 80 goes to nine and the coverage rateis 75%.

It is judged in the ending-condition judgment section 19 whethergeneration situations of the test vector satisfy the ending condition inFIG. 26. For example, since the coverage rate reaches 75% and exceedsthe range of 70% or more as the retrieval condition, it is judged thatthe generation situations of the test vector satisfy the endingcondition. Then, the processing as the test-vector generating method isended. Thereby, paths can be uniformly arranged on the semiconductorintegrated circuit.

Example 3 of the First Embodiment

An example 3 of the first embodiment is a case of an apparatus forgenerating a test vector similar to the apparatus for generating a testvector shown in FIG. 5 describing the second variation of the firstembodiment. In the apparatus for generating a test vector, aretrieval-condition designation section 11 includes, as shown in FIG. 5,a circuit-information setting section 21, a retrieval-priority decisionsection 22, and a circuit-information changing section 23. STEP S13 ofthe test-vector generating method according to the example 1 of thefirst embodiment shown in FIG. 3 is expanded and changed into a step ofa test-vector generating method according to the example 3 of the firstembodiment.

The circuit-information setting section 21 generates circuit-informationset data in a circuit-information set-data region 152 in aretrieval-condition data region 151 as shown in FIG. 30. The datastructure of the circuit-information set data is the same as that of theretrieval condition in FIG. 15.

The retrieval-priority decision section 22 generates priority decisiondata in a priority-decision data region 153 of the retrieval-conditiondata region 151. In the data structure of the priority-decision data,the item data of the circuit-information set data is arranged in theorder of the priority and is associated so that the item data can beretrieved, using the priority. Accordingly, a first retrieval conditionis that the total number of steps for the path is 20 steps or more andthe number of vias is 700 or more. Moreover, a retrieval condition,which is updated after situations where test-vector generation does notsatisfy the ending condition, is only that the total number of steps forthe path is 20 steps or more. Moreover, the retrieval condition afterupdating is only that the number of logic elements is 300 gates or more.Furthermore, the retrieval condition after updating is only that thenumber of vias is 700 or more.

The circuit-information changing section 23 generates thecircuit-information changing data in the circuit information changingdata region 157 of the retrieval-condition data region 151 of theretrieval condition. The data structure of the circuit-informationchanging data includes: an item data region 154; afirst-changing-condition range data region 155; and asecond-changing-condition range data region 156. The item data region154 includes the same item data as that of the item data region in thecircuit-information set data region 152. The first-changing-conditionrange data region 155 is associated so that the first-changing-conditionrange data can be retrieved, using the item data. Thefirst-changing-condition range data is relieved, in comparison with therange data of the circuit-information set data. Accordingly, a retrievalcondition after further updating is that the total number of steps forthe path is 15 steps or more and the number of vias is 500 or more.Similarly, the second changing condition can be applied to the retrievalcondition.

As described above, a set of test vectors which have been finallygenerated are repeatable, not depending on operators, because theretrieval condition is relieved according to a predetermined rule.

Example 4 of the First Embodiment

An example 4 of the first embodiment is a case of an apparatus forgenerating a test vector similar to the apparatus for generating a testvector shown in FIG. 8 describing the fourth variation of the firstembodiment. The apparatus for generating a test vector includes, asshown in FIG. 8: a pin-name-list providing section 25; acircuit-information extraction section 24; a pin-list storage section26; and a circuit-information for each pin-list storage section 27.Generation of a path list at STEP S14 of the test-vector generatingmethod according to example 1 of the first embodiment shown in FIG. 3 isexpanded and changed into that of a test-vector generating methodaccording to example 4 of the first embodiment.

The chip-region designation section 20 designates a region on the chip,or the entire chip area. The pin-name-list providing section 25 makes orcompiles a pin-name list as shown in FIG. 31. The data structure of thepin-name list includes a pin-name data region 158 and a pin-informationdata region 159.

The pin-name data region 158 includes, as pin-name data: a cell name;CLTOP/peace/U268/Z representing the pin name of the cell, and the like.The pin-information data region 159 has pin-information data associatedso that retrieval can be executed using each pin-name data. Thepin-information data is stored in the data region provided for eachitem. The pin-information data includes, as an item: an X coordinate anda Y coordinate of the pin; a wiring length of wiring connected to thepin; and the number of contacts and vias on a signal transmission linein a cell having the pin.

The circuit-information extraction section 24 extracts circuitinformation on the retrieval item for the retrieval condition for eachpin-name list and generates circuit information for each pin list, basedon the pin-name list, and the circuit-information and the retrievalcondition.

Based on the pin-name list and the circuit information for each pinlist, the path-list generation section 14 generates a path list for anew path. It is not required to make a path list, while reading requiredcircuit information from a vast amount of circuit information recordedin the circuit-information storage section 13. The amount of circuitinformation for each pin list can be reduced to a much smaller amount ofinformation than that of the circuit information recorded in thecircuit-information storage section 13. The amount of information can bereduced further, because the circuit information is stored only for thepin-name list.

Example 5 of the First Embodiment

An example 5 of the first embodiment is a case of an apparatus forgenerating a test vector similar to the apparatus for generating a testvector shown in FIG. 9 describing the fifth variation of the firstembodiment. The apparatus for generating a test vector includes, asshown in FIG. 9: a path-circuit-information making section 191; adelimiter-value designation section 195; and a highlighted-pathselection section 193. Generation of a path list at STEP S14 of thetest-vector generating method according to the example 1 of the firstembodiment shown in FIG. 3 is expanded and changed into that of atest-vector generating method according to the example 5 of the firstembodiment.

The circuit-information extraction section 24 generates circuitinformation for each pin list for the retrieval items of the latestretrieval condition after updating, as shown in FIG. 25, of the coveragerate; the total number of steps for the path and the like. Thepath-circuit-information making section 191 compiles circuitinformation, which is limited to the region designated by thechip-region designation section 20, from the circuit information foreach pin list.

The delimiter-value designation section 195 sets a delimiter value shownin FIG. 32 within the set range for the retrieval items of the retrievalcondition in FIG. 25 of the coverage rate and the total number of stepsfor the path. While the coverage rate of the retrieval condition is 70%or more, the delimiter value is set to be 40% or more. While the totalnumber of steps for the path for the retrieval condition is seven stepor more, the delimiter value is set to be five steps or more. The datastructure of the delimiter value has an item data region 160 and a rangedata region 161. The item data region 160 has the coverage rate and thenumber of steps for a path as item data. The range data region 161includes range data associated with item data so that the range data canbe retrieved using each item data. The coverage rate is associated witha range of 40% or more. And the number of steps is associated with arange of five steps.

The highlighted-path selection section 193 generates a path-list for apath satisfying the delimiter value, based on the circuit informationfor each retrieval item. As shown in FIG. 33, a path 164, which is notwithin the range of seven steps or more for a retrieval item of a numberof steps for the path and belongs to a zone with a delimiter value offive steps or more, is highlighted so that the path is distinguishedfrom paths 162, 163 satisfying the retrieval condition. A guideline forsetting the ending condition once again can be easily obtained byretrieving and displaying the path 164 satisfying the delimiter valuewhen the ending condition is not satisfied.

Example 1 of the Second Embodiment

In a fault analysis method of the semiconductor integrated circuitaccording to an example 1 of the second embodiment, a test executionsection 41 executes a delay fault test for the semiconductor integratedcircuit at STEP S31, as shown in FIG. 11. When a fail path is generatedin the test, the test execution section 41 makes a test result shown inFIG. 34 at STEP S32. The data structure of the test result has a dataregion 165 so that a computer can write and read data.

The data region 165 includes as data: a serial number of a test such asTest NO. 701; a distinguishable display number of a test vector used fora test such as Pattern Name: Pat1; Pass for the success of a path orFail for a failed path; delay time measured in a test of Delay Time,such as Delay Time=7.5 nsec; and the like.

Then, a cell-list generation section 43 inputs circuit information onthe semiconductor integrated circuit from the circuit-informationstorage section 33 at STEP S33. At STEP S34, the section 43 generates acell list shown in FIG. 35 for a failed path of a test vector with adistinguishable display number, Pattern Name, of Pat2, based on the testresult and the circuit information.

The data structure of the cell list includes a circuit-identifier-namedata region 166 for a cell and a cell-name data region 167. In thecircuit-identifier-name data region 166 for a cell, the names ofcircuit-identifiers for cells forming a fail path are arranged in theorder of signal transmission of cells. The wiring length of a signaltransmission line of cells and the like can be retrieved as circuitinformation, using the names of circuit-identifiers for cells. In thecell-name data region 167, cell names of cells forming a fail path arearranged in the order of signal transmission of the cells.

At STEP S35, a retrieval-condition designation section 31 generates aretrieval condition, as shown in FIG. 36, for fault-cell searching,wherein the condition retrieves a path sharing a part of the fail path.The data structure of the retrieval condition for fault-cell searchingincludes a retrieval-condition-item data region 168 and a range dataregion 169. The item data region 168 includes, as item data: the numberof sharing steps; the wiring length; and the number of vias for a path.The range data region 169 includes a range data associated with itemdata so that the range data can be retrieved using each item data. Thenumber of sharing steps is associated with a range of three steps ormore. The wiring length is associated with a range of 1.5 mm or more.And the number of vias for the path is associated with a range of 30vias or more.

At STEP S36, the ending-condition designation section 32 generates anending condition for fault-cell searching as shown in FIG. 37. The datastructure of the ending condition for fault-cell searching includes anending-condition-item data region 170 and a range data region 171. Theitem data region 170 includes, as item data: the sharing rate of a path;and the number of test vectors. The sharing rate of a path means a rateof the total number of cell steps of a fail path to the number of cellsteps of a fail path which shares cell steps with a path for fault-cellsearching. The range data region 171 has range data associated with itemdata so that range data can be retrieved using each item data. Thesharing rate of a path is associated with a range of 80% or more. Andthe number of test vectors is associated with a range of 10 or more.

At STEP S37, the path-list generation section 34 generates a path list,as shown in FIG. 38, for fault-cell searching for a path, which satisfysthe retrieval condition, for fault-cell searching, based on the celllist of the fail path. The path-list for fault-cell searching has apath-list data region 172 so that a computer can write and read data.The path-list data region 172 includes a distinguishable display numberof path 2 for a path as leading-line data: Path 2-1. The path-list dataregion 172 includes a distinguishable display number of (GFD2EX2) for acell as cell-line data: Cell 2-1. Similarly, the path-list data region172 includes a distinguishable display number for a cell with regard tocells of Cell 2-2 through Cell 2-9. The Cell 2-1 through Cell 2-9 arearranged in the order of signal transmission of the path of path2. It isunderstood that the path of path2 has nine steps hereafter. The path ofpath2 satisfys the retrieval condition in FIG. 36 that the number ofsharing steps for the path is three steps or more.

It is judged at STEP S38 whether a new path list for the path isextracted. Since a path list for a new path of path2 is generated, theprocessing proceeds to STEP S39. At STEP S39, the test-vector generationsection 36 generates a test vector for fault-cell searching and vectorgeneration information for each path in the path list for fault-cellsearching. According to the vector-generation information, parts ofpaths 174, 175 for the generated test vector for fault-cell searchinghave a shared part of a fail path 173, as shown in FIG. 39. Sharingcells exist in the above sharing part.

It is judged in the ending-condition judgment section 39 at STEP S40whether the vector generation information in FIG. 39 satisfys the endingcondition for fault-cell searching in FIG. 37. At STEP S41, theprocessing returns to STEP S35, because it is judged from thevector-generation information in FIG. 39 that the sharing rate of thepath does not reach 80%, and the number of the test vectors is two anddoes not reach ten.

At STEP S35, the retrieval-condition designation section 31 updates theretrieval condition to a new retrieval condition for fault-cellsearching. A new path, which satisfys the updated retrieval conditionfor fault-cell searching is retrieved to generate a path-list and a testvector for the path for fault-cell searching. When the vector generationinformation satisfies the ending condition for fault-cell searching, thegenerated test vector is output to an external memory.

As described above, the test-vector generating method for fault analysisof the delay fault path can be highly automated by generating the testvector of the path for fault-cell searching, based on the cell list ofthe fail path, the retrieval condition for fault-cell searching, and theending condition. Furthermore, the quality of the generated test vectorfor fault-cell searching can be improved to be much more uniform.

Example 2 of the Second Embodiment

A fault analysis apparatus of the semiconductor integrated circuitaccording to an example 2 of the second embodiment is provided with apin-coordinate storage section 51, as shown in FIG. 13.

The cell-list generation section 43 generates pin-coordinateinformation, as shown in FIG. 40, of an input/output pin of a cellforming a fail path, based on the placing and routing of layoutinformation of the cell. The pin-coordinate storage section 51 storesthe pin-coordinate information. The pin-coordinate information includesa cell-list data region 176 for a fail path, and a pin-coordinate dataregion 177 for a cell. The cell-list data region 176 has the names ofcircuit-identifiers for cells forming a cell list. The pin-coordinatedata region 177 for the cells has an X coordinate and a Y coordinateassociated in such a way that retrieval can be performed, using eachcell name.

In the fault analysis technique of the semiconductor integrated circuit,a test method by which electron beams are irradiated on a chip foranalysis of electric potential is simultaneously used in some cases. Inthe above test method, the pin-coordinate information of theinput/output terminal of the cell is indispensable in order to irradiateelectron beams on the input/output pin of the cell. According to theabove test method, the pin-coordinate information is automaticallygenerated as fail-path information.

Example 3 of the Second Embodiment

Input of a retrieval condition at STEP S35 of the fault analysis methodof the semiconductor integrated circuit according to the secondembodiment shown in FIG. 11 is expanded and changed into that of a faultanalysis method of the semiconductor integrated circuit according to anexample 3 of the second embodiment. In a fault analysis apparatus of thesemiconductor integrated circuit according to example 3 of the secondembodiment, a retrieval-condition designation section 31 includes, asshown in FIG. 8: a circuit-information setting section 21; aretrieval-priority decision section 22; and a circuit-informationchanging section 23.

The circuit-information setting section 21 generates circuit-informationset data in a circuit-information set data region 182 of theretrieval-condition data region 181, as shown in FIG. 41. The datastructure of the circuit-information set data includes an item dataregion and a range data region. The item data region includes the numberof sharing steps; the wiring length; and the number of contacts for thepath. The range data region has range data associated with item data sothat the range data can be retrieved using each item data. The number ofsharing steps is associated with a range of five steps or more. Thewiring length is associated with a range of 1 mm or more. And the numberof contacts for the path is associated with a range of 20 contacts ormore.

The retrieval-priority decision section 22 generates priority decisiondata in a priority-decision data region 183 of the retrieval-conditiondata region 181. In the data structure of the priority-decision data,the item data of the circuit-information set data is arranged in theorder of the priority and is associated so that the item data can beretrieved, using the priority. Accordingly, a first retrieval conditionis that the number of sharing steps for the path is five steps or moreand the wiring length is 1 mm or more. Moreover, an updated retrievalcondition is only that a number of sharing steps for the path is fivesteps or more. Furthermore, the retrieval condition after updating isonly that the wiring length is 1 mm or more. Moreover, the retrievalcondition after updating is only that the number of contacts is 20contacts or more.

The circuit-information changing section 23 generates thecircuit-information changing data in the circuit information changingdata region 187 of the retrieval-condition data region 181 of theretrieval condition. The data structure of the circuit-informationchanging data includes: an item data region 184; afirst-changing-condition range data region 185; and asecond-changing-condition range data region 186. The item data region184 includes the same item data as that of the item data region in thecircuit-information set data region 182. The first-changing-conditionrange data region 185 is associated so that the first-changing-conditionrange data can be retrieved, using the item data. Thefirst-changing-condition range data is relieved, in comparison with therange data of the circuit-information set data. Accordingly, a retrievalcondition after further updating is that the number of sharing steps isthree steps or more, the wiring length is 0.5 mm or more, and the numberof contacts for the path is 10 contacts or more. Similarly, the secondchanging condition can be applied to the retrieval condition.

As described above, a set of test vectors which have been finallygenerated can be repeated, not depending on operators, because theretrieval condition is relieved according to a predetermined rule.

At every updating of the retrieval condition, a test vector forfault-cell searching and vector-generation information for each path ina path list for fault-cell searching are generated. According to thevector-generation information, the paths 174, 175 were retrieved for thefail path 173 under the retrieval condition in the circuit-informationset data region 182 and a test vector was generated, as shown in FIG.42. Moreover, the retrieval condition was relieved for updating, a path188 was retrieved under the first changing condition 185 in thecircuit-information changing data region 187, and a test vector wasgenerated.

Thus, a path is retrieved under a suitable condition for fault analysisas a path retrieving method and a test vector is generated. When atemporarily generated test vector is judged to be unsuitable foranalysis, a vector best suited for fault analysis will be obtained byaddition of a test vector after changing a retrieval condition.

Example 4 of the Second Embodiment

In an example 4 of the second embodiment, a fault analysis apparatus ofa semiconductor integrated circuit similar to the fault analysisapparatus of a semiconductor integrated circuit according to the thirdvariant of the second embodiment in FIG. 14 is used.

First, a chip-region designation section 50 reads logic circuitinformation on the semiconductor integrated circuit from acircuit-information storage section 33 and displays an image of a chip61, as shown in FIG. 43. The chip-region designation section 50 dividesthe image of the chip 61 into regions 69 through 80 and generatesdivided-region information including shapes, sizes, and arrangementpositions of the regions 69 through 80. Then, based on thedivided-region information, images of the regions 69 through 80 aresuperposed and displayed on the image of the chip 61. The image of thechip 61 is equally divided to three images in the vertical direction andto four images in the horizontal direction.

Data for a success path 164, i.e., without failure, fail data for failpaths 162, 163 are input to the chip-region designation section 50 froma fail-data storage section 42 and images of physical positions of thesuccessful path 164, the fail paths 162, 163 are displayed on the imageof the chip. The fail paths 162, 163 and the success path 164 aredistinguishably displayed.

By the chip-region designation section 50, covered regions 70, 71, 74,75, 77 through 79 are configured to have a different display color,assuming that a region is defined to be a covered region when the failpaths 162, 163 pass even a part of the region.

By distinguishably displaying the regions 70, 71, 74, 75, 77 through 79,which are covered by the fail paths 162, 163, on the chip, thechip-region designation section 50 requests an operator to designate andinput regions which are desired to be covered with a path for fault-cellsearching. As shown in FIG. 44, the operator inputs the region 71 whichis desired to be covered into the chip-region designation section 50,responding to the request. The chip-region designation section 50outputs the input region 71, which the operator desires to cover, to aretrieval-condition designation section 31. The retrieval-conditiondesignation section 31 sets a new retrieval condition that the region71, which the operator desires to cover, is covered.

Based on the new retrieval condition, a path-list generation section 34retrieves a path 189 for fault-cell searching shown in FIG. 45 andgenerates a path-list for the path 189. A test-vector generation section36 generates a test vector and a vector generation information for thegenerated path-list. The chip-region designation section 50 displays animage of the new path 189 for fault-cell searching, based on thevector-generation information.

Thus, a situation of paths which succeeded in testing and failed paths,and a situation of generation of test-vectors under generation of thetest vectors of paths for fault-cell searching can be displayed. Theoperator can designate a following retrieval condition for path-lists,based on the displayed situations. Thereby, a fault-analysis operationwith high accuracy can be provided, using a set of test vectors whichare finally generated.

Example 5 of the Second Embodiment

Delay fault testing for a path is executed for each chip. A chip-regiondesignation section 50 summarizes pieces of fail information in thetesting for each of the positions at which chips are arranged on a wafer190, and displays the pieces of fail information with the positions ofeach chip on the wafer 190, as shown in FIG. 46. The fail information isthe number of fail paths for each chip on the wafer 190. The operatorcan confirm distribution of fail paths on the wafer 190. For example,seven fail paths are generated in a line: L4 and a row: R3. However, notendency is observed of distribution bias on the entire surface of thewafer 190. Causes for generated fail paths can be estimated, using theexistence or a tendency of the bias. Moreover, instead of direct displayof the number of fail paths, the numbers of fail paths can be dividedinto zones and display colors can be distinguishably changed,corresponding to the zones. Furthermore, the presence of specific failpaths which pass through a plurality of wafers 190 may be listed as failinformation. And, a chip is divided into smaller regions and a number offail paths for each region or a zone corresponding to the number of failpaths can be displayed, in the case of displaying each wafer.

In addition to the above applications, fail information can be displayedfor each lot or for a plurality of lots. That is, fail paths arecollected and counted for each semiconductor integrated circuit to onewafer, each wafer to one lot, or each lot to a plurality of lots. Asemiconductor integrated circuit, a wafer, or a lot may bedistinguishably displayed, corresponding to the counted number.

Thus, according to testing of a plurality of semiconductor integratedcircuits, statistics of measured values of delay time can be collectedfor paths in the logic circuits which are targets of each test vector.Ratios between the measured values and calculated values used for timinganalysis or for simulation at generating test vectors for delay pathtests are obtained and each path may be distinguishably displayed,corresponding to the ratio. Thereby, differences between measured valuesfor a real chip and calculated values used for timing analysis andsimulation can be easily confirmed.

Various modifications will become possible for those skilled in the artafter receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

1. An apparatus for generating a test vector of a semiconductorintegrated circuit, comprising: a retrieval-condition designationsection designating a retrieval condition configured to select a path onwhich a signal can be transmitted in the semiconductor integratedcircuit; a path-list generation section executing a timing analysis ofthe semiconductor integrated circuit based on circuit information of thesemiconductor integrated circuit, retrieving the path satisfying theretrieval condition, and generating a path list in which cells composingthe retrieved path are put in order of executing the timing analysis; atest-vector generation section generating a test vector configured totest a path delay fault of the semiconductor integrated circuit based onthe path list; an ending-condition designation section designating anending condition configured to end generation of the test vector whenthe path in the path list for the test vector is distributed over thesemiconductor integrated circuit; and an ending-condition judgmentsection stopping generation of the path list when the ending conditionis satisfied.
 2. The apparatus as claimed in claim 1, wherein theending-condition designation section comprises: acoverage-judging-condition designation section dividing thesemiconductor integrated circuit into a plurality of regions anddesignating a condition configured to judge that the path covers theregion; and a coverage-rate definition section designating a coveragerate as a ratio of the number of the regions which are judged to becovered to the total number of the regions.
 3. The apparatus as claimedin claim 2, wherein the retrieval-condition designation sectioncomprises a region designation section displaying a screen image of thesemiconductor integrated circuit divided into the regions, requestingdesignation of the region based on the screen image, and designating theretrieval condition by which the path covering the designated region canbe retrieved.
 4. The apparatus as claimed in claim 1, wherein theretrieval-condition designation section comprises a circuit-informationsetting section setting a retrieval item concerning the circuitinformation and a setting range within which the path is retrievedcorresponding to the retrieval item, and the apparatus further comprisesone of: a retrieval-priority decision section deciding priorities amongthe items to be satisfied by the path to be retrieved; and acircuit-information changing section relieving the set range in thecircuit-information setting section and generating the path list whenthe ending condition is not satisfied.
 5. The apparatus as claimed inclaim 1, wherein the retrieval condition includes a circuit-informationcondition having a retrieval item concerning the circuit information anda set value defining a range within which the path is retrievedcorresponding to the retrieval item, and the apparatus further comprisesone of: a retrieval-order condition including priorities among theretrieval items to be satisfied by the path to be retrieved; and acircuit-information changing condition relieving the set value andgenerating the path list when the ending condition is not satisfied. 6.The apparatus as claimed in claim 2, further comprising: a pin-name-listmaking section making a pin-name list extracting pin names of the cellsin the designated regions based on placing and routing of layoutinformation on the cells in the circuit information on the designatedregions; and a circuit-information extraction section extracting thecircuit information of the retrieval items by each of the pin-name list.7. The apparatus as claimed in claim 6, wherein the path-list generationsection executes timing analysis and retrieves a path covering thedesignated regions based on the pin-name list and the circuitinformation for each of the retrieval items.
 8. The apparatus as claimedin claim 6, further comprising: a path-circuit-information makingsection making the circuit information for each of the retrieval itemsof the path covering the designated regions based on the circuitinformation for each of the extracted retrieval items; a delimiter-valuedesignation section setting a delimiter value within the setting rangeand dividing the setting range into a plurality of zones by thedelimiter value; and a distinguished-path displaying sectiondistinguishably displaying the path in each of the zones to which thecircuit information for each of the retrieval items of the path belongsand superposing the path on a screen image of the semiconductorintegrated circuit.
 9. An apparatus for analyzing an failure in asemiconductor integrated circuit, comprising: a cell-list generationsection generating a list of cells composing a path in the semiconductorintegrated circuit with a delay fault based on a test result of whetherthe delay fault is generated on the path; a retrieval-conditiondesignation section designating a retrieval condition configured toretrieve a fault-cell searching path, which includes a part of the pathwith the delay fault; a path-list generation section for fault-cellsearching, which retrieves the fault-cell searching path based on theretrieval condition, and generates a fault-cell searching path list inwhich cells composing the retrieved fault-cell searching path are put inorder of transmitting a signal; a test-vector generation section forfault-cell searching, which generates a test vector based on thefault-cell searching path list; an ending-condition designation sectiondesignating an ending condition configured to end generation of the testvector; and an ending-condition judgment section stopping generation ofthe path list when the ending condition is satisfied.
 10. The apparatusas claimed in claim 9, wherein the ending condition includes at leastone of a condition that a number of generated test vectors exceeds apredetermined number, and a condition that test vectors have tried to begenerated for all of the generated path lists.
 11. The apparatus asclaimed in claim 9, wherein a fail path segment along the screen imageof the path with the delay fault is displayed in a distinguishablemanner from a screen image of the semiconductor integrated circuitincluding a screen image of the path with the delay fault.
 12. Theapparatus as claimed in claim 11, wherein a fault-cell searching pathsegment along the fault-cell searching path is configured to bedistinguished from the screen image of the semiconductor integratedcircuit, the screen image of the path with the delay fault, and the failpath segment.
 13. The apparatus as claimed in claim 9, wherein theretrieval-condition designation section comprises a circuit-informationsetting section setting a retrieval item concerning the circuitinformation and a setting range within which the path is retrievedcorresponding to the retrieval item, and the apparatus further comprisesone of: a retrieval-priority decision section deciding priorities amongthe items to be satisfied by the path to be retrieved; and acircuit-information changing section relieving the set range in thecircuit-information setting section and more easily generating the pathlist when the ending condition is not satisfied.
 14. The apparatus asclaimed in claim 9, wherein the retrieval condition includes acircuit-information condition having a retrieval item concerning thecircuit information and a set value defining a range within which thepath is retrieved corresponding to the retrieval item, and the apparatusfurther comprises one of: a retrieval-order condition includingpriorities among the retrieval items to be satisfied by the path to beretrieved; and a circuit-information changing condition relieving theset value and generating the path list when the ending condition is notsatisfied.
 15. The apparatus as claimed in claim 9, whereinpin-coordinate information of an input/output pin of the cells composingthe path with the delay fault is generated based on a placing androuting of layout information in the circuit information on thesemiconductor integrated circuit.
 16. The apparatus as claimed in claim11, wherein the semiconductor integrated circuit is divided into aplurality of regions, and the regions are displayed and distinguishedfrom each other according to the number of the fault paths with thedelay fault covering the regions respectively.
 17. The apparatus asclaimed in claim 9, wherein numbers of the paths with the delay faultare counted for each semiconductor integrated circuit on one wafer, eachwafer of one lot, or each lot in a plurality of lots, and thesemiconductor integrated circuit, the wafer, or the lot is displayed anddistinguished from each other according to the numbers of paths withdelay faults.
 18. The apparatus as claimed in claim 12, wherein one ofthe fail path segment and the fault-cell searching path segment ishighlighted according to a ratio of one of a measured value of a delaytime for the path with the delay fault and a measured value of a delaytime measured with the test vector to a calculated value of the delaytime respective.
 19. A computer-implemented method for generating a testvector of a semiconductor integrated circuit comprising: designating aretrieval condition configured to select a path on which a signal can betransmitted in the semiconductor integrated circuit; executing a timinganalysis of the semiconductor integrated circuit based on circuitinformation of the semiconductor integrated circuit, retrieving the pathsatisfying the retrieval condition, and generating a path list in whichcells composing the retrieved path are put in order of executing thetiming analysis; generating a test vector configured to test a pathdelay fault of the semiconductor integrated circuit based on the pathlist; designating an ending condition configured to end generation ofthe test vector when the path in the path list for the test vector isdistributed over the semiconductor integrated circuit; and stoppinggeneration of the path list when the ending condition is satisfied. 20.A computer program product to be executed by a computer for generating atest vector of a semiconductor integrated circuit comprising:instructions designating a retrieval condition configured to select apath on which a signal can be transmitted in the semiconductorintegrated circuit; instructions executing a timing analysis of thesemiconductor integrated circuit based on circuit information of thesemiconductor integrated circuit, retrieving the path satisfying theretrieval condition, and generating a path list in which cells composingthe retrieved path are put in order of executing the timing analysis;instructions generating a test vector configured to test a path delayfault of the semiconductor integrated circuit based on the path list;instructions designating an ending condition configured to endgeneration of the test vector when the path in the path list for thetest vector is distributed over the semiconductor integrated circuit;and instructions stopping generation of the path list when the endingcondition is satisfied.